Multi-Gate Transistor Manufacturing with Segmented Insulator Deposition

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Solution Overview

Problem

Existing methods for manufacturing transistors on a single chip with different voltage capabilities face challenges in optimizing gate insulators for various types of transistors, requiring multiple steps and affecting reliability and performance.

Innovation Solution

A method involving sequential deposition of dielectric and polysilicon layers, an interface layer, high permittivity material, and metallic layers, followed by etching and spacer formation to define gates for low-voltage, medium-voltage, and high-voltage transistors, allowing for simultaneous manufacturing with minimal additional steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If different gate insulator formation methods are used for different transistor types, then each transistor type can have optimized gate insulator characteristics, but the manufacturing process complexity increases

Engineering Contradiction:

Improvetransistor performance and reliabilityVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The manufacturing process is segmented into distinct processing sequences for different transistor types. Low-voltage transistors receive thin gate insulators formed early in the process, while high-voltage transistors receive thick gate insulators formed later, allowing each type to have optimized characteristics without compromising the other

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The gate insulator for low-voltage transistors is formed preliminarily before the gate insulator for high-voltage transistors. This preliminary action allows the thin gate insulator to be established first, then protected or isolated while the thick gate insulator for high-voltage transistors is formed in subsequent steps

Inventive Principle:

Principle #10Preliminary action

2Reliability

If multiple separate manufacturing processes are used for different transistor types, then each transistor type can be optimized independently, but the number of manufacturing steps increases

Engineering Contradiction:

Improvetransistor optimizationVSAvoidnumber of manufacturing steps

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

Multiple transistor types are merged into a single integrated manufacturing process. The process combines common steps (such as substrate preparation and initial layer deposition) with divergent steps that create different gate insulator configurations, reducing the total number of separate manufacturing sequences needed

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Different regions of the semiconductor substrate receive different gate insulator thicknesses and compositions tailored to local requirements. Low-voltage transistor regions receive thin gate insulators while high-voltage transistor regions receive thick gate insulators, with the differentiation achieved through localized processing steps rather than separate full-wafer processes

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the co-integration of transistors with optimized gate insulators, ensuring high reliability and performance by maintaining the integrity of high-voltage transistor gate insulators while allowing for different voltage capabilities, and simplifying the manufacturing process.

Implementation Method 1

depositing a first dielectric layer and a first polysilicon layer on the third areas; depositing a second dielectric layer on the second areas; depositing an interface layer on the first areas; depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; depositing a second polysilicon layer on the first, second, and third areas

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

etching all the way to the first dielectric layer into the third areas to define gates; etching all the way to the semiconductor material first and second areas to define gates

Methodology Applied

Scientific EffectPlasma Etching: Plasma

Data Source

PatentUS10332808B2Device comprising multiple gate structures and method of simultaneously manufacturing different transistors

Publication Date: 2019.06.25 STMICROELECTRONICS (CROLLES 2) SAS

AI summary

A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.