Multi-gate Transistor Sidewall Contacts for Channel Control
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Solution Overview
Problem
Multi-gate FETs face challenges with short channel length and contact length in gate pitch, leading to performance limitations and increased variability.
Innovation Solution
A method for fabricating multi-gate transistors with plurality of sidewall contacts, involving forming a semiconductor fin, etching a trench, depositing an oxide material, forming a spacer dielectric layer, removing the dummy oxide layer, and creating a high-k material liner and metal gate stack, which results in a curved channel region and sidewall contacts along the metal gate stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional multi-gate FET structure is used, then manufacturing process is simple, but channel length is short and variability increases
Solution Approach 1:
The invention segments the single gate structure into multiple gates (e.g., top gate and sidewall gates) that wrap around the channel region. This segmentation allows each gate to contribute to channel control, effectively increasing the controlled channel length while maintaining manufacturability through standardized fabrication processes
Solution Approach 2:
The invention transitions from a planar 2D gate structure to a 3D multi-dimensional gate configuration where gates are positioned on multiple surfaces (top and sidewalls) of the channel. This dimensional change increases the effective gate-controlled channel length without proportionally increasing the footprint area
2Productivity
If gate pitch is reduced for scaling, then device density increases, but contact length becomes short and performance degrades
Solution Approach 1:
The invention introduces sidewall contacts that extend vertically along the sidewalls of the channel region, adding a vertical dimension to the contact structure. This allows the contact length to increase in the vertical direction while the horizontal gate pitch remains small, thereby maintaining high device density without sacrificing contact length
Solution Approach 2:
The sidewall contacts are nested within the three-dimensional structure formed by the trenches and channel regions, utilizing the vertical space efficiently. This nested configuration allows multiple contacts to be packed closely in the horizontal plane while maintaining sufficient vertical contact length for reliable electrical connection
3Ease of manufacture
If conventional contact structure is used, then process is simple, but parasitic resistance is high due to 3D spreading resistance
Solution Approach 1:
The invention segments the contact structure into multiple sidewall contacts distributed along the channel sidewalls rather than a single large contact. This segmentation creates multiple parallel current paths that reduce the 3D spreading resistance while maintaining a relatively simple fabrication process using standard etching and deposition techniques
Data Source
AI summary
A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.