Multi-Gate Transistor Structure with Vertical Gate Terminals
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Solution Overview
Problem
The precise and uniform fabrication of metal contacts under the gate terminals of transistors with multiple gate terminals is challenging, especially in highly scaled electronic devices, leading to variability in contact position and increased resistance and parasitic capacitances, which hinders the dense integration of transistors and affects the performance of integrated circuits.
Innovation Solution
The use of independent multiple gate contacts adjacent to a common channel with metal-to-semiconductor contacts at the channel ends, where the gate terminals are separated by dielectric spacers and extended into a third dimension, allowing for precise control of channel conductivity and reducing contact resistance and parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal contacts are formed under multiple gate terminals in highly scaled devices, then transistor integration density increases, but contact position variability increases and contact resistance increases
Solution Approach 1:
The patent extends gate terminals into a third dimension (vertical dimension) by forming raised gate structures that protrude toward the metal contacts. This dimensional change allows better spatial separation and alignment between multiple gate terminals and their corresponding metal contacts, reducing position variability while maintaining high integration density.
Solution Approach 2:
The patent divides the gate terminal structure into multiple independent gate segments, each with its own metal contact. This segmentation allows independent optimization and alignment of each gate-contact pair, reducing the cumulative position variability that would occur with monolithic multi-gate structures.
2Productivity
If metal contacts are formed under multiple gate terminals in highly scaled devices, then transistor integration density increases, but parasitic capacitances increase
Solution Approach 1:
The patent extracts and separates the gate terminal structures from each other by introducing dielectric materials between adjacent gates. This spatial separation reduces the overlapping electric fields between gates, thereby reducing parasitic capacitances while maintaining high integration density through vertical extension.
Solution Approach 2:
The patent introduces dielectric materials as intermediary layers between adjacent gate terminals and between gate terminals and metal contacts. These intermediary dielectric layers act as electrical insulators that reduce capacitive coupling, thereby reducing parasitic capacitances while allowing close spatial proximity for high density integration.
3Ease of manufacture
If conventional metal contact fabrication is used under multiple gate terminals, then manufacturing process simplicity is maintained, but contact resistance increases
Solution Approach 1:
The patent performs preliminary formation of raised gate structures and dielectric spacers before final metal contact deposition. This preliminary structuring creates pre-defined alignment features and controlled contact areas, ensuring low contact resistance through optimized contact geometry while maintaining compatibility with standard fabrication processes.
Solution Approach 2:
The patent changes the geometric parameters of the metal contacts by forming raised gate structures that create larger and more controlled contact areas. This parameter change (increased contact area through vertical extension) reduces contact resistance while the processes remain compatible with conventional fabrication methodologies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable and scalable integration of transistors with reduced contact resistance and parasitic capacitances, enhancing the performance and reliability of integrated circuits by allowing for precise control of channel conductivity and efficient network formation within a single transistor.
Implementation Method 1
gate terminals are separated by dielectric spacers and extended into a third dimension
Implementation Method 2
These contacts can be either Ohmic, e.g. in the case of a band-to-band tunneling field effect transistors, or characterized by a Schottky barrier
Implementation Method 3
These contacts can be either Ohmic, e.g. in the case of a band-to-band tunneling field effect transistors, or characterized by a Schottky barrier
Implementation Method 4
The electrical conduction in the channel of a MOSFET is fixed by doping providing electron (n-type) or hole (p-type) conduction. The channel conductivity of the MOSFET is adjusted by the voltage applied to the gate terminal
Data Source
AI summary
One example provides an integrated circuit comprising a transistor including a semiconductor channel. The semiconductor channel includes three or more sub-channels, one or more nodes, each node being a junction of at least three sub-channels, and channel ends. A Schottky contact at each channel end forms a source or drain contact, and a gate contact disposed at each Schottky contact controls a barrier conductivity of the corresponding Schottky contact.