Multi-Gate VVA Circuit for High Linearity and Power Handling

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Solution Overview

Problem

Conventional Voltage Variable Attenuators (VVAs) face limitations in linearity and power handling due to process technology constraints, which restrict their performance.

Innovation Solution

A high linear voltage variable attenuator design utilizing series transistor elements and shunt circuits with multiple gates, controlled by bias signals to achieve attenuation, optimized for low insertion loss, low power consumption, and cost-effective implementation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multi-gate MESFETs or pHEMTs are used in each arm to improve power handling and linearity, then power handling and linearity performance are improved, but device complexity increases and process technology flexibility is reduced

Engineering Contradiction:
Improvelinearity performanceVSAvoidtransistor gate structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The VVA is divided into multiple arms (typically three arms in a T-topology or Pi-topology configuration), with each arm containing series transistor elements and shunt circuits. This segmentation allows the linearity enhancement function to be distributed across multiple simpler transistor elements rather than requiring complex multi-gate transistors in each arm, thereby improving linearity performance while managing device complexity.

Inventive Principle:
Principle #1Segmentation

2Power

If multi-gate MESFETs or pHEMTs are used in each arm to improve power handling and linearity, then power handling capability is improved, but device complexity and manufacturing constraints increase

Engineering Contradiction:
Improvepower handling capabilityVSAvoidtransistor gate structure
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The power handling function is segmented across multiple arms and multiple transistor elements within each arm. By using several series transistor elements with controlled impedances rather than a single complex multi-gate transistor, the patent achieves high power handling capability while avoiding the manufacturing constraints and complexity associated with multi-gate transistor fabrication.

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If conventional VVA topology is used, then basic attenuation function is achieved, but linearity is limited by process technology constraints

Engineering Contradiction:
Improveattenuation controlVSAvoidlinearity performance
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent employs dynamic control of variable impedances in each arm through bias signals applied to the series transistor elements and shunt circuits. This dynamic adjustment capability allows the VVA to maintain high linearity performance across different attenuation levels by optimally configuring the impedance states of individual transistor elements, overcoming the static limitations of conventional VVA topologies constrained by fixed process technology parameters.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8614597B2High linear voltage variable attenuator (VVA)
Publication Date: 2013.12.24 MACOM TECH SOLUTIONS HLDG INC
  • US8614597B2 patent drawing
  • US8614597B2 patent drawing
  • US8614597B2 patent drawing

AI summary

An apparatus comprising one or more series transistor network elements and a plurality of shunt circuits. The series transistor network may be configured to generate an output signal in response to (i) an input signal, (ii) a first bias signal, and (iii) a plurality of variable impedances. The plurality of shunt circuits may each be configured to generate a respective one of the variable impedances in response to a second bias signal. The output signal may have an attenuation that is equal to or less than the input power. The amount of the attenuation may be controlled by the first bias signal and the second bias signal. The series transistor elements and the plurality of shunt circuits may be configured as two or more transistors each having two or more gates.