Multi-Gate Metal Gate Stack Layout for Tight GAA Trench Space
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for fabricating gate-all-around (GAA) transistors face challenges in depositing work function layers to achieve different threshold voltages due to limited vertical space between channels, particularly affecting n-type field effect transistors (NFETs) in semiconductor devices like Static Random Access Memory (SRAM), requiring stringent process control.
Innovation Solution
The method involves forming n-type work function layers for NFETs before p-type work function layers, allowing p-type layers to fine-tune n-type layers, thereby improving device performance by enabling different threshold voltages for various regions of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If work function layers are deposited to achieve different threshold voltages for NFETs and PFETs, then device performance is improved, but the vertical space between channels is filled, leaving limited room in gate trenches and requiring stringent process control
Solution Approach 1:
The patent applies preliminary action by forming the n-type work function layer first, before forming the p-type work function layer. This sequential approach allows the n-type layer to be deposited and partially fill the vertical space between channels, while the p-type layer is then deposited to fine-tune the threshold voltage. This preliminary formation of the n-type layer simplifies the overall process control by establishing a baseline structure that guides subsequent deposition steps.
Solution Approach 2:
The patent applies local quality by creating different work function layer configurations for different device regions. The n-type work function layer is formed in both NFET and PFET regions, but the p-type work function layer is selectively formed only in PFET regions. This allows each region to have locally optimized properties: NFETs rely on the n-type layer for threshold voltage control, while PFETs use the combination of n-type and p-type layers for fine-tuned control.
2Manufacturing precision
If work function layers wrap adjacent stacked nanostructures, then threshold voltage can be controlled, but vertical space is consumed, leaving limited room in gate trenches
Solution Approach 1:
The n-type work function layer is formed as a preliminary structure that wraps the stacked nanostructures and fills vertical space. This preliminary layer establishes the basic threshold voltage control mechanism. Subsequently, the p-type work function layer is deposited to provide additional fine-tuning capability without requiring complete re-deposition of the entire work function structure, thereby preserving some gate trench space.
Solution Approach 2:
The patent applies the nested doll principle by having the p-type work function layer deposited on top of and surrounding the n-type work function layer. The n-type layer forms an inner structure that wraps the channels, while the p-type layer forms an outer structure that provides additional control. This nested configuration allows both layers to contribute to threshold voltage control while optimizing the use of vertical space within the gate trench.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by allowing for precise tuning of threshold voltages, particularly in NFETs, improving the functionality of semiconductor devices such as SRAMs.
Implementation Method 1
the depositing of the p-type work function layer increases an oxygen concentration in the n-type work function layer
Data Source
AI summary
A method includes providing a structure having a first stack of nanostructures spaced vertically one from another and a second stack of nanostructures spaced vertically one from another, forming a dielectric layer wrapping around each of the nanostructures in the first and second stacks, depositing an n-type work function layer on the dielectric layer and a p-type work function layer on the n-type work function layer and over the first and second stacks. The n-type work function layer wraps around each of the nanostructures in the first stack. The p-type work function layer wraps around each of the nanostructures in the second stack. The method also includes forming an electrode layer on the p-type work function layer and over the first and second stacks.