Multi-Gated I/O Power-On Sequencing to Prevent Ramp-Up Glitches
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Solution Overview
Problem
Integrated circuit (IC) I/O circuits face glitches during power ramp-up due to undesired signal transitions, leading to instability in output and input signals, which affects the reliability of electrical connections.
Innovation Solution
A system for generating gated power-on control signals that uses a multi-gated I/O interface with a gating signals generator to control the enabling of output and input level shifters and drivers sequentially, ensuring signal stabilization before enabling subsequent components, thereby preventing glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power ramp-up is performed in I/O circuit, then power supply is established, but signal glitches occur due to undesired transitions
Solution Approach 1:
The patent applies preliminary action by enabling the output level shifter before the output driver, and enabling the input buffer before the input level shifter during power ramp-up. This sequential enabling ensures that level shifting is completed before drivers are activated, preventing glitches caused by premature signal transitions. The gating signals generator produces carefully timed enable signals that prepare the circuit path in advance before actual data transmission begins.
2Device complexity
If single-gated I/O interface is used, then device complexity is reduced, but signal stabilization cannot be ensured during power ramp-up
Solution Approach 1:
The patent segments the I/O interface into multiple controllable stages: output level shifter, output driver, input buffer, and input level shifter. Each stage is independently controlled by separate gating signals (POC1, POC2, POC3, POC4) generated by the gating signals generator. This segmentation allows precise control over the activation sequence of each component, ensuring that level shifters are enabled before drivers and buffers, thereby stabilizing signals during power ramp-up while maintaining manageable device complexity through systematic organization.
Data Source
AI summary
A method of operating a power-on (PO) signal generator (which generates a PO signal and includes a supply-variation sensitivity-reducing (SVSR) load coupled between a first reference voltage and a first node, and a first transistor coupled between the first node and a second reference voltage, the SVSR load including a first resistor coupled between the first reference voltage and a second node, and a second transistor coupled between the second node and the first node, each of a control input of the SVSR load and a gate terminal the first transistor being coupled to a monitored voltage) includes: when the monitored voltage rises above a threshold voltage of the first transistor, turning on the first transistor, and pulling first and second voltages correspondingly on the first and second nodes, a third voltage of the second transistor, and the PO signal down to a logical low value.