Multi-GPU Interconnect Architecture for Scalable Rendering
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Solution Overview
Problem
Existing graphics processing systems face challenges in improving performance while maintaining manufacturable scale and power density, particularly in distributing 3D graphics rendering processes across multiple GPU chips due to complex dependence/reference relationships and limited software development capabilities.
Innovation Solution
A graphics processor configuration with a command processor, geometry engine, and bus fabric connected to memory, featuring interconnects that allow data transfer and access between multiple GPUs and a shared memory space, enabling coordinated operation as a single virtual GPU.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple GPU chips are used to improve performance, then processing capability is improved, but device complexity increases due to dependence/reference relationships and software distribution difficulties
Solution Approach 1:
The system is segmented into multiple GPU chips (first GPU chip, second GPU chip, etc.), each with its own local memory, while introducing a master GPU chip that coordinates the segmented components. This segmentation enables performance improvement through parallel processing while managing complexity through hierarchical organization.
Solution Approach 2:
The master GPU chip acts as an intermediary between the CPU and slave GPU chips, managing task distribution, memory coordination, and data flow. This intermediary resolves the complexity of direct multi-GPU coordination by centralizing control logic in a single coordinating unit.
2Productivity
If one large-capacity memory is shared by CPU and GPU chip (UMA), then processing efficiency is improved, but manufacturable scale is limited
Solution Approach 1:
Instead of using one large-capacity memory on a single chip, the memory is segmented across multiple GPU chips, each with its own local memory capacity. This segmentation enables the system to achieve large total memory capacity while maintaining manufacturable individual chip scales.
Solution Approach 2:
The memory architecture transitions from a single-dimension (one large memory on one chip) to a multi-dimensional structure where multiple smaller memories are distributed across multiple chips, accessible through the master GPU chip's coordination mechanism.
3Productivity
If multiple GPU chips are used, then processing capability is improved, but power density increases beyond acceptable limits
Solution Approach 1:
The master GPU chip selectively activates slave GPU chips based on task requirements, rather than continuously operating all chips at full capacity. This partial action approach improves processing capability when needed while reducing overall power consumption during lighter workloads.
Data Source
AI summary
A graphics processor having a command processor and a geometry engine and connected to a memory and another graphics processor includes a bus fabric that delivers and receives data to and from the memory connected thereto, and a first interconnect that is connected to the command processor and the geometry engine and that delivers and receives data to and from a command processor and a geometry engine of the other graphics processor. Via a second interconnect, the bus fabric delivers and receives data to and from a bus fabric of the other graphics processor, and is accessibly connected to a memory connected to the other graphics processor.