Multi-GPU Interface Unit for Data Transfer Efficiency

The patent introduces an interface unit as an intermediary component between the general-purpose processor and the graphics processor. This interface unit includes a write FIFO queue that receives out-of-order commands from the general-purpose processor and a read double buffer that stores commands for in-order execution. The intermediary structure translates the out-of-order command stream into an in-order execution stream, allowing the graphics processor to execute commands correctly while maintaining high data transfer efficiency from the general-purpose processor.

The patent segments the command processing into two distinct paths: a write FIFO queue for in-order command storage and a read double buffer for out-of-order command retrieval. The write FIFO ensures that commands are written to the graphics processor in the correct sequence, maintaining data integrity. The read double buffer allows the general-purpose processor to read commands out-of-order for faster processing. This segmentation separates the concerns of command ordering and data transfer speed, resolving the contradiction between them.

The interface unit serves multiple functions simultaneously: it acts as a FIFO queue for write commands, a double buffer for read commands, and a command translation mechanism between out-of-order and in-order execution modes. By combining these functions into a single interface unit, the patent maintains system flexibility through the I/O interface connection while achieving high data communication efficiency through optimized buffering and translation operations.