Multi-GPU Scheduling for Deterministic Latency and Thermal Balance

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Solution Overview

Problem

Current parallel graphics data processing systems face challenges in achieving deterministic scheduling across multiple general-purpose graphics processing units (GPUs), leading to inconsistent latency and performance variability.

Innovation Solution

A multi-GPU architecture with uniform latency is implemented, along with techniques to distribute memory output based on memory chip thermals, enable thermally aware workload scheduling, and negotiate end-to-end contracts for workload scheduling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If parallel graphics data processing is implemented across multiple GPUs, then processing throughput is improved, but latency consistency deteriorates

Engineering Contradiction:
Improveprocessing throughputVSAvoidlatency consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the graphics processing workload into distinct operation types (compute operations, memory operations, I/O operations) and assigns them to different GPU clusters or processing streams. This segmentation allows each segment to be handled with optimized scheduling policies, ensuring that critical operations maintain deterministic latency while non-critical operations maximize throughput, thus resolving the contradiction between productivity and latency consistency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic scheduling mechanisms that adjust operation assignment and resource allocation in real-time based on system state, workload characteristics, and performance targets. The scheduler dynamically modifies processing paths, memory allocation, and inter-GPU communication patterns to maintain consistent latency across varying throughput conditions, enabling the system to adaptively balance productivity and latency consistency.

Inventive Principle:
Principle #15Dynamics

2Productivity

If workload is distributed across multiple memory chips, then processing capacity is improved, but thermal management difficulty increases

Engineering Contradiction:
Improveprocessing capacityVSAvoidthermal management difficulty
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent applies local quality by implementing chip-level and region-level thermal awareness in the scheduling decisions. Different memory chips or regions are assigned different workload characteristics based on their thermal state, power capacity, and cooling efficiency. The system can direct heat-generating operations to chips with better thermal headroom while minimizing workload on thermally constrained chips, thus maintaining processing capacity while managing thermal distribution across the multi-chip system.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent incorporates thermal feedback mechanisms that continuously monitor temperature, power consumption, and thermal throttling events across memory chips. This feedback informs the scheduler to dynamically adjust workload distribution, preventing thermal runaway and ensuring reliable operation. The feedback loop enables the system to maintain optimal processing capacity while adapting to changing thermal conditions in real-time.

Inventive Principle:
Principle #23Feedback

3Reliability

If deterministic scheduling is implemented, then latency consistency is improved, but system complexity increases

Engineering Contradiction:
Improvelatency consistencyVSAvoidscheduling system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent achieves deterministic scheduling by changing key parameters of the graphics operations, including priority levels, timing constraints, and resource allocation parameters. By formally specifying these parameters and using them to drive scheduling decisions, the system can guarantee latency consistency without requiring complex adaptive algorithms. The parameter-based approach provides a structured framework that simplifies the scheduling logic while maintaining deterministic performance.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250028675A1Graphics processor operation scheduling for deterministic latency
Publication Date: 2025.01.23 INTEL CORP
  • US20250028675A1 patent drawing
  • US20250028675A1 patent drawing
  • US20250028675A1 patent drawing

AI summary

Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.