Multi-GPU Memory Management With Unified Cache Coherency

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Solution Overview

Problem

Current techniques for managing storage in machine learning systems face inefficiencies, particularly in achieving coherency across multiple GPUs, which leads to significant overhead and inefficiency in data transfer, and lack precision in memory usage during neural network tasks.

Innovation Solution

A novel technique is introduced that provides a unified memory view for multiple GPUs, enabling cache coherency and efficient data transfer through a consumer-producer model, adaptive quality of trained networks, and computation in high-bandwidth memory (HBM) to improve data locality and reduce unnecessary data movement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If coherency protocols are added across GPU links to achieve cache coherency, then cache coherency is improved, but system overhead increases significantly

Engineering Contradiction:
Improvecache coherencyVSAvoidsystem overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a unified memory management unit (MMU) as an intermediary that mediates memory access requests between multiple GPUs and the host processor. This central化的管理机制 coordinates memory operations across GPU links without requiring complex distributed coherency protocols, thereby achieving cache coherency while minimizing system overhead.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The unified memory architecture allows the same physical memory to be accessed by multiple GPUs and the host processor simultaneously through a common address space. This multi-functional memory system eliminates the need for separate memory copies and complex coherency management, reducing overhead while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of operation

If data is transferred across multiple GPUs using conventional techniques, then data transfer is enabled, but efficiency deteriorates due to large overhead

Engineering Contradiction:
Improvedata transfer capabilityVSAvoiddata transfer efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent merges multiple GPU memory spaces into a unified address space that can be accessed by all GPUs and the host processor. This consolidation allows efficient data sharing and transfer without the overhead of traditional inter-GPU communication protocols, significantly improving data transfer efficiency while maintaining ease of operation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The unified memory architecture transitions from a distributed memory model (separate memory spaces per GPU) to a unified memory model (single address space). This dimensional change in memory organization enables more efficient data access patterns and reduces the overhead associated with cross-GPU data transfer.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If high capacity networks are used for machine learning, then network capacity is improved, but training efficiency deteriorates due to storage management inefficiencies

Engineering Contradiction:
Improvenetwork capacityVSAvoidtraining efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The unified memory management system performs preliminary allocation and organization of data in a unified address space before training operations begin. This pre-organization of data eliminates the need for inefficient data movement and copying during training, allowing high capacity networks to operate at full efficiency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11592817B2Storage management for machine learning at autonomous machines
Publication Date: 2023.02.28 INTEL CORP
  • US11592817B2 patent drawing
  • US11592817B2 patent drawing
  • US11592817B2 patent drawing

AI summary

A mechanism is described for facilitating storage management for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting one or more components associated with machine learning, where the one or more components include memory and a processor coupled to the memory, and where the processor includes a graphics processor. The method may further include allocating a storage portion of the memory and a hardware portion of the processor to a machine learning training set, where the storage and hardware portions are precise for implementation and processing of the training set.