Multi-grained Writeback Cache Defragmentation via Hierarchical Metadata

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Solution Overview

Problem

Conventional caching systems face challenges in maintaining consistency and scalability when handling small random writes in distributed storage systems, particularly in scaling metadata memory footprint for non-volatile memory write caches, which are essential for high workload density demands.

Innovation Solution

A multi-grained metadata model with cache management mechanisms that utilize cache block descriptors (CBDs) and fine block descriptors (FBDs) to minimize metadata memory footprint, maximize NVM utilization, and enhance back-end disk performance, allowing for efficient defragmentation of fragmented cache blocks to maintain data consistency and scalability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If server-side caching is used to handle small random writes, then write performance is improved, but metadata memory footprint scaling becomes difficult

Engineering Contradiction:
Improvewrite performanceVSAvoidmetadata memory footprint
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments the cache address space into multiple regions, each with its own metadata structures. This allows the system to manage metadata in distributed chunks rather than requiring a single large metadata structure, enabling scalable memory footprint management while maintaining server-side caching capabilities for small random writes

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical metadata organization structure with multiple levels of abstraction. By adding dimensional organization to metadata management (e.g., region-level, block-level descriptors), the system can scale metadata memory footprint efficiently without compromising write performance

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If fine-grained updates are implemented for cache address space, then random write absorption is improved, but cache utilization becomes fragmented

Engineering Contradiction:
Improverandom write absorptionVSAvoidcache utilization
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent dynamically adjusts granularities of cache block descriptors based on workload characteristics and cache state. By changing parameters such as block size and descriptor granularity adaptively, the system maintains fine-grained update capability while reducing fragmentation through coarser-grained operations when appropriate

Inventive Principle:
Principle #35Parameter changes

3Stability of the object's composition

If defragmentation operations are performed on fragmented CBDs, then cache organization is improved, but I/O operations are delayed

Engineering Contradiction:
Improvecache organizationVSAvoidI/O latency
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

The patent implements periodic or background defragmentation operations rather than immediate defragmentation upon detecting fragmentation. This allows normal I/O operations to proceed without interruption while defragmentation is performed during low-utilization periods or in the background, maintaining cache organization without significant I/O latency impact

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent performs preliminary consolidation of cache blocks during write operations when space is available, rather than waiting for fragmentation to occur and then defragmenting. This preliminary action reduces the need for subsequent defragmentation operations and minimizes I/O delays

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9965390B2Reducing defragmentation in a multi-grained writeback cache
Publication Date: 2018.05.08 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9965390B2 patent drawing
  • US9965390B2 patent drawing
  • US9965390B2 patent drawing

AI summary

In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to select a cache block descriptor (CBD) from amongst a plurality of CBDs, the selected CBD including indications of being fragmented in the cache storage device. The logic is also configured to determine whether to defragment the selected CBD. Moreover, the logic is configured to defragment the selected CBD on the cache storage device in response to a decision to defragment the selected CBD.