Multi-granularity Parallel Storage System for Matrix Data
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Solution Overview
Problem
Conventional on-chip storage systems are unable to perform parallel read/write operations on matrix data in rows and columns simultaneously, leading to inefficiencies in signal processing systems that require simultaneous operations across different data types and granularities.
Innovation Solution
A multi-granularity parallel storage system is designed with a shift generator, address increment lookup unit, address shifter, row address generator, and address adders to generate appropriate addresses for multiple memory units, allowing for parallel read/write operations across different data types and granularities, eliminating the need for transposition operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory is designed to read/write in parallel multiple elements in a row, then row parallel read/write capability is improved, but column parallel read/write capability deteriorates
Solution Approach 1:
The memory system is segmented into multiple independent memory banks (first memory bank and second memory bank), each capable of independent row parallel read/write operations. This segmentation allows the system to perform row operations on one bank while simultaneously performing column operations on another bank, thereby resolving the contradiction between row parallel capability and column parallel capability.
Solution Approach 2:
The patent introduces a new dimension of operation by enabling column parallel read/write through a transposition mechanism that operates across memory banks. Instead of limiting the memory to a single row-oriented or column-oriented mode, the system adds a temporal and spatial dimension by using multiple banks to execute different operation types simultaneously, thus achieving both row and column parallel capabilities.
2Device complexity
If the memory uses fixed bit width R/W ports, then hardware complexity is reduced, but adaptability to different data types deteriorates
Solution Approach 1:
The memory system achieves multi-functionality by implementing a unified memory architecture that can handle multiple data types (bytes, short words, integers, floating-point numbers) through a single set of R/W ports. The system uses data type identification and corresponding data processing circuits to universally support different granularities without requiring separate hardware for each data type, thus maintaining low hardware complexity while achieving high adaptability.
Solution Approach 2:
The system changes the parameter of data granularity dynamically based on the identified data type. When a byte is identified, the system processes 8 bits; when a short word is identified, it processes 16 bits; and so on. This parameter change approach allows the fixed bit width R/W ports to adapt to different data types by adjusting the processing granularity through control logic and data reorganization circuits.
3Device complexity
If the memory sequentially addresses data, then addressing logic is simplified, but parallel access efficiency deteriorates
Solution Approach 1:
The addressing logic is segmented into row address generation and column address generation components that operate independently and in parallel. The row address generator produces row addresses for row-oriented access, while the column address generator produces column addresses for column-oriented access. This segmentation allows both types of parallel access to occur simultaneously without increasing overall system complexity, as each segment handles its specific addressing task efficiently.
Data Source
AI summary
A multi-granularity parallel storage system including a plurality of memories, a shift generator, an address increment lookup unit, an address shifter, a row address generator, and a plurality of address adders. The shift generator is configured to generate a shift value. The address increment lookup unit is configured to generate input data for the address shifter. The address shifter is configured to cyclically shift the input data rightward by Shift elements and then output the shifted data. The row address generator is configured to generate a row address RowAddr and input the generated row address RowAddr to the other input terminal of each address adder. Each address adder is configured to perform a non-sign addition of the input data at the two input terminals to obtain a read/write (R/W) address for one of the memories and input the R/W address to an address input terminal of the memory.