Multi-granularity Parallel Storage for Matrix Data
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Solution Overview
Problem
Conventional on-chip storage systems are unable to perform parallel read/write operations on matrix data in rows and columns simultaneously, leading to inefficiencies in signal processing systems that require simultaneous operations across different data types and granularities.
Innovation Solution
A multi-granularity parallel storage system with a memory read/write port and a data gating network that allows for concurrent read/write operations across multiple memory blocks, enabling parallel access to matrix data in rows and columns by selecting and concatenating memory units based on address and granularity, thereby supporting different data types and granularities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory is designed with fixed R/W ports and sequential addressing, then the memory structure is simple and easy to manufacture, but it cannot perform parallel read/write operations on both rows and columns of matrix data simultaneously
Solution Approach 1:
The memory is divided into multiple memory blocks (e.g., 4 blocks) that can be independently accessed. Each block can be selectively activated based on whether row-wise or column-wise parallel access is needed, allowing the system to achieve parallel read/write capabilities while keeping individual block structures relatively simple.
Solution Approach 2:
The memory system dynamically switches between different access modes (row-wise parallel access or column-wise parallel access) based on computational requirements. Control logic selectively enables different memory blocks and adjusts addressing schemes in real-time, providing adaptive parallel access without requiring a permanently complex structure for both modes simultaneously.
2Adaptability or versatility
If the memory uses a single data type per memory unit, then the memory design is simplified, but it cannot efficiently handle matrices with different data types (byte, short word, integer, floating-point) requiring different read/write granularities
Solution Approach 1:
The memory system is designed to universally handle multiple data types (8-bit byte, 16-bit short word, 32-bit integer, 64-bit floating-point) using the same physical memory structure. By varying the read/write granularity and addressing scheme rather than creating separate memory structures for each data type, the system achieves multi-functionality while controlling complexity.
Solution Approach 2:
The system changes parameters such as read/write granularity (1, 2, 4, or 8 memory units) and addressing stride to adapt to different data type requirements. For example, 32-bit integers use a granularity of 4 with appropriate byte-offset addressing, while 64-bit floating-point values use a granularity of 8, allowing flexible data type support through parameter adjustment rather than structural complexity.
3Productivity
If the memory provides only row-wise parallel access, then the memory structure remains simple, but signal processing algorithms requiring column-wise parallel access (e.g., matrix multiplication) cannot be efficiently executed
Solution Approach 1:
The memory system inverts the conventional approach by enabling both row-wise and column-wise parallel access through the same physical structure. By using control logic to selectively activate different memory blocks and adjust addressing modes, the system provides column-wise access capability without requiring a transposed memory structure, thus maintaining simplicity while achieving the needed functionality.
4Productivity
If multiple memory blocks are used to enable multi-granularity access, then parallel read/write capability is improved, but the control logic and data gating network become more complex
Solution Approach 1:
The control logic is designed to pre-select and activate only the necessary memory blocks based on the access pattern requirements before data transfer begins. By preliminarily configuring which blocks are active and what granularity to use, the system minimizes the complexity of simultaneous control signals while enabling concurrent access to multiple blocks with different granularities.
Data Source
AI summary
A multi-granularity parallel storage system includes an R/W port and a memory. The memory includes W memory blocks and a data gating network. Each of the memory blocks is a 2D array consisting of multiple memory units, and each memory row of the 2D array includes W memory units. For each memory block, one memory row can be read/written at a time, W is the nth power of 2, and n is a natural number.