Multi-Grooved Interposer for 3D Chip Assembly
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Solution Overview
Problem
Prior art interposers face thermal budget limitations and are constrained in attaching multiple semiconductor chips due to the size compatibility issue, limiting their usefulness in constructing three-dimensional chip assembly structures.
Innovation Solution
A multi-grooved interposer with parallel grooves and conductive strips is used, allowing semiconductor chips to be partially inserted and electrically contacted, overcoming thermal budget constraints and enabling the attachment of more than two chips per interposer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If prior art flat interposers with C4 bonding are used, then electrical connection between chips is achieved, but the number of chips that can be attached is limited to two due to size compatibility constraints
Solution Approach 1:
The patent transitions from a planar interposer architecture to a three-dimensional vertical interposer structure. The vertical interposer enables chips to be stacked in multiple layers rather than arranged in a single plane, fundamentally changing the spatial dimension of chip integration. This allows significantly more chips to be attached to a single interposer by utilizing vertical space, directly resolving the limitation of only being able to attach two chips with prior art flat interposers.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked vertically within the space occupied by a single interposer. Each chip is positioned at a different vertical level, with conductive vias extending through the interposer to establish electrical connections between chips at different heights. This nesting approach maximizes the use of available space and enables high-density chip integration.
2Quantity of substance
If prior art interposers are used, then chip assembly is achieved, but thermal budget limitations prevent attachment of multiple chips
Solution Approach 1:
The patent divides the chip assembly process into multiple independent bonding stages. Instead of attempting to bond all chips simultaneously to the interposer (which would exceed thermal budget limits), the process bonds chips one at a time or in small groups. Each bonding operation uses a controlled, limited thermal budget, and subsequent chips are bonded to already-attached chips rather than directly to the interposer, thereby distributing the thermal load across multiple lower-temperature processes.
Solution Approach 2:
The patent performs preliminary bonding operations to attach the first chip to the interposer before proceeding to attach additional chips. This staged approach allows the system to establish a stable base connection first, then build upon it with subsequent chip attachments. By preparing and bonding chips in a predetermined sequence rather than simultaneously, the thermal budget for each individual bonding step remains manageable.
3Adaptability or versatility
If flat interposers with different bonding pad array configurations are used, then size and pitch differences between chips are accommodated, but device complexity increases
Solution Approach 1:
The vertical interposer design provides a universal interface structure that can accommodate multiple different chip types and configurations. The standardized vertical via pattern and bonding pad arrangement on the interposer can interface with various chip bonding pad layouts through appropriate via routing and pad mapping. This multi-functional design reduces the need for custom-interposer designs for each chip type, thereby reducing overall device complexity while maintaining adaptability.
Data Source
AI summary
A multi-grooved interposer includes an interposer substrate containing multiple parallel grooves laterally extending along a first direction and laterally spaced among one another along a second direction, and multiple conductive strips. The multiple parallel grooves are recessed from front side surfaces of the multi-grooved interposer in a third direction toward a back side surface of the multi-grooved interposer. The multiple conductive strips continuously extend across recessed surfaces in the multiple parallel grooves and the front side surfaces along the second direction with an undulating surface profile to provide electrically conductive paths across the multiple parallel grooves. Each of the multiple parallel grooves is configured to receive an edge of a respective semiconductor chip.