Multi-group pad arrangement for narrow bezel display driver
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Solution Overview
Problem
The challenge in display devices is to reduce the height of the fan-out area in a bezel of a display screen, particularly for large resolution displays with a narrow bezel, where a large number of hard wires need to access a small edge area, making it difficult to maintain a thin bezel width.
Innovation Solution
The solution involves a new output pad sequence design on a driver chip disposed in proximity to the fan-out area, where interconnects are routed to access pads from side edges rather than directly from the top edge, reducing the fan-out area height and bezel width by using multiple driver chips and optimizing the routing of interconnects across multiple edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large number of hard wires are routed from the display area to access the electrical circuit in the bezel, then the electrical connections are established, but the height of the fan-out area and the width of the bezel increase
Solution Approach 1:
The patent applies dimensionality change by routing interconnects through multiple edges of the driver chip rather than concentrating all connections at a single edge. Specifically, interconnects are routed from the first edge, second edge, and third edge of the driver chip to different subsets of pads, effectively utilizing the three-dimensional space around the chip to reduce the two-dimensional fan-out area height and bezel width.
Solution Approach 2:
The patent segments the pad connections into multiple groups based on their routing paths. The pads are divided into first subset of pads accessible from the first edge, second subset of pads accessible from the second edge, and third subset of pads accessible from the third edge. This segmentation allows interconnects to be distributed across multiple edges, reducing the concentration of wires at any single location and thereby reducing fan-out area height.
2Area of moving object
If the resolution of the display screen is increased to provide large screen real estate, then the display quality is improved, but the number of hard wires required increases, making it difficult to maintain a narrow bezel
Solution Approach 1:
The patent resolves the increased routing complexity from high-resolution displays by utilizing multiple edges of the driver chip for interconnect routing. Instead of all interconnects competing for space at a single edge, the system distributes connections across the first, second, and third edges, effectively using three-dimensional space to manage the complexity of routing numerous wires for high-resolution screens.
Solution Approach 2:
The patent segments the large number of interconnects required for high-resolution displays into multiple groups, each accessing different subsets of pads through different edges of the driver chip. This segmentation reduces the local density of interconnects at each edge, making the routing more manageable despite the overall increase in connection数量 due to higher resolution.
3Ease of manufacture
If all interconnects are routed from a single edge of the driver chip, then the routing is simple, but the fan-out area height increases
Solution Approach 1:
The patent moves from a one-dimensional routing approach (all interconnects from a single edge) to a three-dimensional routing approach utilizing multiple edges of the driver chip. Interconnects are routed from the first edge to a first subset of pads, from the second edge to a second subset of pads, and from the third edge to a third subset of pads, thereby distributing the routing load and reducing fan-out area height.
Solution Approach 2:
The patent segments the pad access points into multiple locations around the driver chip perimeter. Instead of all pads being accessible from one edge, the pads are divided into subsets accessible from different edges, which segments the interconnect routing paths and reduces the concentration of wires in any single region, thereby reducing fan-out area height.
Data Source
AI summary
An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area has interconnects providing electrical accesses to display elements of the display area. The device has a driver chip disposed on the driver area. The driver chip includes a first edge adjacent to the display area and multiple pad groups, each pad group including a respective row of electronic pads that is (i) arranged substantially in parallel with the first edge and (ii) electrically coupled to a respective subset of display elements via respective interconnects routed on a respective region of the fan-out area. The pad groups include a first pad group and a second pad group. The first and second pad groups have two different distances from the first edge and correspond to two different subsets of interconnects routed on two non-overlapping regions of the fan-out area.