Multi-Hash Table Lookup With Overflow Memory and Bounded Latency
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Solution Overview
Problem
Content Addressable Memories (CAMs) are expensive in terms of chip area and power consumption, making them impractical for many applications, and existing hash table solutions do not provide efficient data search in packet-based communication nodes.
Innovation Solution
A hash table system with multiple hash tables, an overflow memory, and a weighted round-robin arbiter that manages key-value pair operations, including update, match, and rehash commands, to optimize chip area and power consumption while ensuring rapid data search.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CAM is used for rapid data search, then search speed is improved, but chip area and power consumption increase
Solution Approach 1:
The patent replaces expensive CAM with SRAM-based hash tables that use standard memory cells instead of complex CAM circuitry. The hash table uses simple comparison logic and linear probing to achieve lookup functionality without requiring the expensive CAM architecture, thereby reducing chip area while maintaining acceptable search performance.
Solution Approach 2:
The patent substitutes the mechanical/CAM-based parallel comparison approach with a software-driven hash table implementation using SRAM. The hash function computes indices deterministically, and linear probing sequentially searches for matches, replacing the need for complex CAM hardware with simpler memory and control logic.
2Speed
If CAM is used for rapid data search, then search speed is improved, but power consumption increases
Solution Approach 1:
The patent replaces power-hungry CAM with SRAM-based hash tables that consume less power. SRAM cells require significantly less power than CAM circuitry, and the hash table's sequential access pattern with linear probing reduces overall power consumption compared to CAM's parallel comparison mechanism.
3Area of stationary object
If traditional hash table lookup engine is used, then chip area and power consumption are reduced, but search efficiency decreases
Solution Approach 1:
The patent applies hash functions to compute lookup indices before the actual search begins, directing searches to specific locations in the hash table. This preliminary hashing action significantly reduces the average search space compared to linear search, improving search efficiency while using standard SRAM memory.
Solution Approach 2:
The patent uses multiple hash functions and dynamic resizing parameters to optimize hash table performance. By adjusting the number of hash functions, table size, and probing strategy, the system achieves high search efficiency adaptable to different workload characteristics while maintaining area efficiency.
4Speed
If multiple hash tables are used for rapid lookup, then lookup speed is improved, but device complexity increases
Solution Approach 1:
The patent divides the hash table into multiple segments or uses multiple hash functions that map to different regions. This segmentation allows parallel processing of hash computations and reduces collision interference, improving lookup speed while keeping each individual hash table component simple and manageable.
Solution Approach 2:
The patent implements a unified hash table data structure that handles multiple operations (insertion, deletion, lookup) through the same underlying mechanism. The same hash function and linear probing logic serve all operations, reducing overall system complexity compared to having separate specialized structures for each operation.
Data Source
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AI summary
A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.