Multi-Height Capacitance Cells for Semiconductor Noise Suppression

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Solution Overview

Problem

The standard cell method in semiconductor devices limits the ability to create large capacitance regions, as capacitance cells must adhere to standardized dimensions, making it difficult to achieve sufficient capacitance for noise suppression in semiconductor devices.

Innovation Solution

The semiconductor device incorporates multi-height capacitance cells with cell heights of two or more times the distance between power lines, featuring overlapping gate electrodes and diffusion regions aligned in a continuous well of a different conductivity type, allowing for increased capacitance areas and improved noise suppression.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the standard cell method is used to structure capacitance cells, then the cell dimensions are standardized and layout consistency is improved, but the capacitance area is reduced and insufficient capacitance for noise suppression occurs

Engineering Contradiction:
Improvecell dimension standardizationVSAvoidcapacitance area
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent extends the capacitance cell structure in the vertical direction by creating multi-height cells with overlapping gate electrodes at different levels. This dimensional extension allows the capacitance area to exceed the constraints of standardized horizontal cell dimensions, resolving the contradiction between standardization and sufficient capacitance area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested gate electrode structures where multiple gate electrodes are positioned at different heights and overlap vertically. The gate electrodes are arranged in a nested configuration within the same planar footprint but at different elevation levels, effectively multiplying the capacitance area without increasing the standardized cell dimension.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If multi-height capacitance cells with overlapping gate electrodes are used, then the capacitance area is increased, but the cell structure complexity is increased

Engineering Contradiction:
Improvecapacitance areaVSAvoidcell structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the capacitance cell into multiple height segments with gate electrodes positioned at different levels. Each segment can be independently formed through separate fabrication steps, allowing the complex multi-height structure to be constructed systematically rather than as a monolithic complex structure, thereby managing the complexity while achieving increased capacitance area.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances capacitance efficiency by increasing the ratio of capacitance area to total cell area, effectively suppressing noise fluctuations in semiconductor devices.

Implementation Method 1

a capacitance cell including a diffusion region of a first conductivity type and a gate electrode stacked above the diffusion region, and functioning as a decoupling capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11532545B2Semiconductor device
Publication Date: 2022.12.20 KK TOSHIBA
  • US11532545B2 patent drawing
  • US11532545B2 patent drawing
  • US11532545B2 patent drawing

AI summary

A semiconductor device of an embodiment includes: a plurality of power lines extending in a first direction; and a plurality of cells arrayed along the first direction and a second direction intersecting the first direction and having a cell height of an integer multiple of a distance between the power lines adjacent to each other in the second direction, the cell height being a dimension in the second direction, wherein the plurality of cells include: a functional cell that contributes to a function of the semiconductor device; and a capacitance cell including a diffusion region of a first conductivity type and a gate electrode stacked above the diffusion region, and functioning as a decoupling capacitor, the capacitance cell is configured as a multi-height cell having a cell height of two or more times the distance, the capacitance cell includes a plurality of overlapping regions that are regions of the gate electrode overlapping the diffusion region in a stacking direction, the overlapping regions being aligned in the second direction, and the plurality of overlapping regions are arranged in one continuous well of a second conductivity type different from the first conductivity type.