Multi-Height Standard Cell Layout for Routing Space and Lower Power
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Solution Overview
Problem
Existing integrated circuits face challenges in efficiently routing operations between standard cells due to limitations in layout design and metal layer utilization, leading to increased power consumption and area requirements.
Innovation Solution
The implementation of multi-height standard cells with symmetric circuit regions and input pins in different metal layers, allowing for optimized routing and reduced metal layer usage, thereby improving operating performance and securing routing space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard cells are arranged in conventional layouts, then routing operations between standard cells become complex and power consumption increases, but the layout design and metal layer utilization are limited
Solution Approach 1:
The standard cell is divided into multiple circuit regions (first circuit region, second circuit region, third circuit region) arranged in different rows. Each region contains specific transistors and input pins, allowing independent routing and optimization of signal paths between regions, thereby simplifying the overall routing operation while maintaining functional integrity.
Solution Approach 2:
The patent utilizes multiple rows (first row, second row, third row) to arrange circuit regions vertically, adding a dimensional aspect to the layout. Input pins are distributed across different rows and metal layers, enabling routing operations to proceed more efficiently by utilizing vertical space and multiple metal layers rather than being constrained to a single-plane layout.
2Area of stationary object
If conventional metal layer usage is applied, then routing space is insufficient and power consumption increases, but metal layer utilization is limited
Solution Approach 1:
The patent distributes input pins across multiple metal layers (first metal layer, second metal layer, third metal layer) and multiple rows. This vertical distribution enables routing operations to utilize multiple metal layers for signal transmission, increasing routing space capacity and reducing congestion in any single layer, thereby lowering power consumption associated with signal routing.
Solution Approach 2:
Different circuit regions are assigned to different metal layers based on their specific functions and routing requirements. The first circuit region uses the first metal layer, the second circuit region uses the second metal layer, and the third circuit region uses the third metal layer, allowing optimized local routing for each region while distributing the overall routing load across multiple layers.
3Ease of operation
If standard cell height is fixed, then manufacturing is simplified, but routing operations with other standard cells become difficult
Solution Approach 1:
The standard cell is segmented into multiple rows with different heights, allowing each row to be optimized for specific routing operations. The first row, second row, and third row can be manufactured using standardized processes while accommodating different vertical dimensions, enabling flexible routing operations with other standard cells without requiring complete redesign of the manufacturing process.
Data Source
AI summary
A standard cell and an integrated circuit including the same are is provided. The standard cell is provided in first and second rows. The standard cell includes: a first circuit region provided in the first row and including a plurality of first transistors; a second circuit region provided in the second row and including a plurality of second transistors; a first input pin provided in the first circuit region and configured to receive a first input signal; and a second input pin provided in the second circuit region and configured to receive a second input signal. The first input signal is input to gate terminals of each of the plurality of first transistors, and the second input signal is input to gate terminals of each of the plurality of second transistors. The first circuit region is symmetric with respect to a second horizontal direction and the second circuit region is symmetric with respect to the second horizontal direction.