Multi-Height Standard Cells for Low-Parasitic Nanosheet ICs
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate transistors like tri-gate transistors, is compounded by the trade-off between critical feature dimensions and spacing constraints in lithographic processes, leading to increased parasitic capacitance and resistance.
Innovation Solution
Implementing multi-height low-parasitic high-drive standard cells with innovative power rail configurations and partial nanosheet power scaling techniques, such as mixing rows of taller and shorter standard cells with varying nanosheet populations, to optimize device performance and reduce parasitic capacitance without scaling cell size or gate pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to increase density, then the number of functional units increases, but parasitic capacitance and resistance increase
Solution Approach 1:
The patent introduces multi-height cell structures that extend vertically across multiple standard cell heights (e.g., 2x, 3x, 4x, 5x heights). This vertical dimensionality change allows functional units to be stacked above one another, increasing the number of functional units per planar area while maintaining controlled parasitic effects through the vertical arrangement and shared power rail configurations.
Solution Approach 2:
The patent merges multiple standard cell heights into unified multi-height cell structures with shared power rails. By combining adjacent cells of the same type across multiple heights and sharing power distribution networks, the design reduces redundant parasitic elements and optimizes power delivery while increasing functional unit density.
2Reliability
If multi-gate transistors are used to improve short channel control, then device performance improves, but lithographic spacing constraints become more severe
Solution Approach 1:
The patent employs multi-gate transistor structures (such as tri-gate or gate-all-around configurations) that utilize vertical gating dimensions to enhance short channel control. The gate structure wraps around the channel from multiple sides, providing superior electrostatic control without requiring proportionally smaller lithographic features, thus resolving the spacing constraint issue.
Solution Approach 2:
The patent uses composite material structures in the transistor design, combining different semiconductor materials (e.g., SiGe source/drain regions with silicon channel) and dielectric materials with varying properties to optimize both short channel control and lithographic manufacturability. The composite structure allows tailored electrical characteristics while maintaining feasible fabrication dimensions.
3Area of stationary object
If cell size is reduced to increase density, then area decreases, but performance in critical speedpaths deteriorates
Solution Approach 1:
The patent creates multi-height cell structures that extend vertically to provide additional drive strength for critical speedpath cells. By stacking transistor layers vertically within multi-height cells, the effective channel width and drive current are increased without expanding the planar footprint, thus maintaining high performance in critical paths while preserving area efficiency.
Solution Approach 2:
The patent applies different cell height configurations selectively: standard single-height cells are used for non-critical paths where area is paramount, while multi-height cells (2x, 3x, 4x, or 5x heights) are deployed in critical speedpaths where performance is prioritized. This local differentiation optimizes the overall design by matching cell characteristics to functional requirements.
Data Source
AI summary
Integrated circuit structures having multi-height cells, and methods of fabricating integrated circuit structures having multi-height cells, are described. For example, an integrated circuit structure includes a single height cell in a block, and a multi-height cell in the block, the multi-height cell having a single NMOS diffusion area and a single PMOS diffusion area, and the multi-height cell having a power rail above the single NMOS diffusion area and the single PMOS diffusion area, where the power rail is not shared between the multi-height cell and the single height cell. Another integrated circuit structure includes a row of relatively taller cells with relatively wider 2-stack nanosheets, and a row of relatively shorter cells with relatively narrower 2-stack nanosheet, the row of relatively shorter cells coupled to the row of relatively taller cells.