Multi-Height CFET Cell Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The increasing downsizing of integrated circuits poses challenges for standard cells, leading to issues such as high parasitic capacitance and degraded performance due to the proximity of input and output metal lines, which are not effectively addressed by existing designs.
Innovation Solution
The implementation of Complementary Field-Effect Transistors (CFETs) with double-height structures separates input and output metal lines, reducing parasitic capacitance and improving signal routing efficiency by using vertically stacked FETs with separate channel regions for lower and upper transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard cells are downsized to increase integration density, then the number of circuits per die increases, but parasitic capacitance between input and output metal lines increases and performance degrades
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical routing by stacking FETs in multiple heights. Input and output metal lines are routed on different vertical levels, separating them spatially to reduce parasitic capacitance while maintaining high integration density through efficient use of vertical space
Solution Approach 2:
The standard cell is divided into multiple height segments (single-height and double-height cells) with distinct routing regions. This segmentation allows input and output lines to be separated across different vertical levels, reducing capacitive coupling while preserving integration density through optimized cell placement
2Productivity
If standard cells are downsized to increase integration density, then the number of circuits per die increases, but signal routing becomes more difficult and resistance increases
Solution Approach 1:
The patent introduces vertical routing dimensions to accommodate signal paths that would be congested in planar layouts. By stacking FETs and routing metal lines on different vertical levels, the design achieves shorter, lower-resistance signal paths while maintaining high integration density
Solution Approach 2:
The patent implements flexible cell height configurations (single-height and double-height cells) that can be dynamically selected based on routing requirements. This dynamic adaptability allows optimization of signal paths for minimal resistance while maintaining overall integration density
3Area of stationary object
If input and output metal lines are placed close together to reduce cell size, then integration density increases, but parasitic capacitance increases and speed decreases
Solution Approach 1:
The patent separates input and output metal lines along the vertical dimension while maintaining close horizontal proximity for compact cell area. This three-dimensional arrangement reduces parasitic capacitance and improves signal speed without sacrificing integration density
Solution Approach 2:
The patent applies different height configurations to different regions of the standard cell. Double-height cells are used where vertical separation is needed for high-speed signals, while single-height cells maintain compact area, achieving local optimization of both speed and integration density
Data Source
AI summary
A structure includes a standard cell, which includes a first single-height part and a second single-height part. The first single-height part comprises a first VDD line, a first VSS line, and a first input metal line. The second single-height part is abutting the first single-height part to form an interface. The second single-height part comprises a second VDD line, a second VSS line, and an output metal line. In a top view of the structure, the first input metal line and the output metal line have lengthwise directions parallel to the interface.