Multi-Height Contact Regions for Low-Parasitic-Capacitance Transistors
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Solution Overview
Problem
As semiconductor fabrication technology advances, the increasing parasitic capacitance between source/drain contact regions and the metal gate in transistors hinders device speed and power consumption, preventing further scaling of semiconductor devices.
Innovation Solution
The semiconductor device design includes contact regions with specific height variations, where one portion of each contact region is recessed to reduce the surface area in contact with the metal gate, thereby minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate spacer widths are reduced to increase transistor integration density, then more transistors can be integrated into a single semiconductor device, but parasitic capacitance between source/drain contact regions and metal gate increases
Solution Approach 1:
The patent applies dimensionality change by forming contact regions with varying heights (first portion at first height, second portion at second height) to reduce parasitic capacitance. This vertical dimensional variation allows the contact regions to maintain electrical connectivity while minimizing overlapping area with the metal gate, thereby reducing parasitic capacitance without affecting horizontal integration density.
Solution Approach 2:
The contact regions are segmented into multiple portions with different heights. The first portion extends to a first height and the second portion extends to a second height, creating distinct segments that serve different functions. This segmentation allows optimization of each portion's contribution to electrical connection while minimizing parasitic capacitance formation area.
2Speed
If parasitic capacitance is reduced through contact region design, then device speed increases and power consumption decreases, but fabrication process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the contact regions with specific height variations before forming the metal gate. The contact regions are prepared in advance with their multi-level structure, which then facilitates easier formation of the metal gate with reduced parasitic capacitance. This preliminary structuring of contact regions simplifies subsequent fabrication steps while achieving the desired low parasitic capacitance outcome.
Data Source
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AI summary
A semiconductor device with low parasitic capacitance comprises a substrate. The semiconductor device also comprises a gate region on the substrate. The semiconductor device further comprises a contact region on the substrate, wherein the contact region comprises a first portion and a second portion, wherein the first portion is in contact with the substrate and has a first surface above the substrate, and wherein the second portion is in contact with the substrate and has a second surface above the substrate different from the first surface.