Multi-Height IC Interconnects for Lower Resistance and Capacitance
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Solution Overview
Problem
The increasing density of transistor architectures in integrated circuits (ICs) leads to higher parasitic electrical resistance and capacitance in metallization features, resulting in higher power consumption and degraded performance due to the scaling down of interconnect density and aspect ratios.
Innovation Solution
The implementation of multi-height vias and lines in IC interconnect levels, where taller vias contact shorter lines and shorter vias contact taller lines, allows for independent tuning of resistance and capacitance, achieved through subtractive patterning of conductive material layers, enabling self-aligned fabrication and reduced parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional etch and fill paradigm is used to increase interconnect density, then transistor density increases, but parasitic electrical resistance and capacitance increase leading to higher power consumption
Solution Approach 1:
The interconnect structure is segmented into multiple height levels (first height and second height) within the same interconnect level. This segmentation allows different regions to have optimized resistance and capacitance characteristics, enabling independent tuning of electrical properties to reduce overall power consumption while maintaining high interconnect density.
Solution Approach 2:
The patent introduces vertical dimensionality by creating multi-height vias and lines within a single interconnect level. Instead of only increasing density through planar scaling, the solution utilizes the vertical dimension to create taller and shorter conductive features, adding a new degree of freedom for optimizing electrical characteristics without further increasing parasitic effects.
2Productivity
If metallization features are scaled down to increase interconnect density, then more interconnects fit in the same area, but parasitic resistance increases degrading performance
Solution Approach 1:
Different regions of the interconnect level are assigned different heights (first height and second height) based on local electrical performance requirements. This local quality differentiation allows critical performance paths to use optimized height dimensions while maintaining overall high interconnect density, thus preserving reliability across the entire circuit.
Solution Approach 2:
The patent changes the geometric parameter of via and line heights to optimize electrical performance. By providing multiple height options (first height and second height) for vias and lines, the design can adjust resistance and capacitance parameters independently in different regions, maintaining performance reliability while achieving higher interconnect density.
3Reliability
If multi-height vias and lines are implemented to independently tune resistance and capacitance, then performance is optimized, but fabrication complexity increases
Solution Approach 1:
The formation of multi-height vias and lines is merged with the existing subtractive patterning process used for underlying interconnect lines. By integrating via formation into the line patterning sequence and using the same etch and fill operations, the patent achieves multi-height structures without proportionally increasing fabrication complexity, thus maintaining performance optimization while controlling manufacturing complexity.
Solution Approach 2:
The subtractive patterning process is designed to automatically create self-aligned vias and lines. The etch process selectively removes material to form both lines and vias in a single operation, and the fill process automatically deposits conductive material into all formed features. This self-service approach reduces the need for additional alignment and patterning steps, thereby controlling fabrication complexity while achieving performance optimization.
Data Source
AI summary
Integrated circuitry comprising an interconnect level with multi-height lines contacted by complementary multi-height vias. In some examples, a first line of a taller height is contacted by a first via of a shorter height while a second line of a shorter height is contacted by a second via of a taller height. The first and second vias and first and second lines may be subtractively defined concurrently from a same stack of conductive material layers such that the first via comprises a first conductive material layer, and the first line comprises second and third conductive material layers while the second via comprises the first and second conductive material layers and the second line comprises the third conductive material layer.