Multi-Height Interconnect Metallization for Intra-Layer RC Tuning
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Solution Overview
Problem
As integrated circuit (IC) transistor density increases, interconnect parasitics such as resistance-capacitance (RC) delay become a significant challenge due to the density of interconnect metallization structures, and simply increasing the cross-sectional area of metallization lines to reduce resistance can lead to process complexity and performance loss.
Innovation Solution
The fabrication of metallization lines with different heights within a single interconnect level using a hardmask material layer and trench mask pattern, allowing for controlled resistance and capacitance optimization through varying trench depths and widths, while maintaining a planar top surface for reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cross-sectional area of metallization lines is increased to reduce resistance, then resistance is reduced, but process complexity increases and performance loss occurs due to edge placement errors
Solution Approach 1:
The patent applies local quality by creating metallization lines with different heights within the same interconnect level. Specifically, first line metallization has a first height while second line metallization has a second height greater than the first height. This allows different cross-sectional areas for different lines, enabling resistance optimization for specific lines without increasing overall process complexity. The selective height adjustment targets only the lines that need resistance reduction.
Solution Approach 2:
The patent introduces height as an additional dimension for resistance control within a single interconnect level. By varying the height (vertical dimension) of metallization lines while keeping them coplanar at the top surface, the invention enables resistance tuning without adding more interconnect levels. This dimensional approach allows resistance optimization through cross-sectional area variation without proportionally increasing process complexity.
2Reliability
If multiple height interconnects are used to enable intra-layer R&C optimization, then resistance and capacitance are optimized, but process complexity is disproportionately increased resulting in additional cost and performance loss
Solution Approach 1:
The patent implements local quality by selectively creating different metallization heights only where needed for R&C optimization. The first line metallization maintains a first height while the second line metallization has a second height, allowing tailored resistance and capacitance characteristics for different interconnect lines within the same level without requiring all lines to have multiple height variations.
Solution Approach 2:
The patent applies parameter changes by varying the height parameter of metallization lines to optimize resistance and capacitance. The first line metallization has a first height and the second line metallization has a second height greater than the first height, enabling independent tuning of electrical parameters (R&C) for different lines while maintaining a coplanar top surface for manufacturing simplicity.
3Reliability
If metallization lines of differing heights are created within a single interconnect level, then intra-layer R&C optimization is achieved, but edge placement errors increase due to added process complexity
Solution Approach 1:
The patent applies local quality by creating height variations only in specific metallization lines where R&C optimization is needed, while other lines maintain the standard height. This localized approach minimizes the impact on edge placement accuracy compared to applying multiple height variations across all lines. The first and second line metallization have different heights only where required, preserving manufacturing precision for the majority of the interconnect structure.
Solution Approach 2:
The patent uses the height dimension to achieve R&C optimization while maintaining coplanar top surfaces for all metallization lines. This dimensional approach allows vertical variation without compromising the horizontal alignment and edge placement accuracy that would be affected by adding more interconnect levels or complex lateral variations.
Data Source
AI summary
Integrated circuit metallization lines having a planar top surface but different vertical heights, for example to control intra-layer resistance/capacitance of integrated circuit interconnect. A hardmask material layer may be inserted between two thicknesses of dielectric material that are over a via metallization. Following deposition of the hardmask material layer, trench openings may be patterned through the hardmask layer to define where line metallization will have a greater height. Following the deposition of a thickness of dielectric material over the hardmask material layer, a trench pattern may be etched through the uppermost thickness of dielectric material, exposing the hardmask material layer wherever the trench does not coincide with an opening in the hardmask material layer. The trench etch may be retarded where the hardmask material layer is exposed, resulting to trenches of differing depth. Trenches of differing depth may be filled with metallization and then planarized.