Multi-Height Interconnect Trenches for Resistance-Capacitance Tradeoffs
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Solution Overview
Problem
Existing semiconductor interconnect layers with uniform interconnect heights face a tradeoff between resistance and capacitance, where reducing resistance increases capacitance and vice versa, leading to a balance that compromises either delay or power efficiency.
Innovation Solution
The implementation of interconnect layers with multi-height interconnect trenches allows for optimized signal paths by routing delay-critical paths along taller interconnects and other paths along shorter interconnects, thereby achieving low resistance and low capacitance simultaneously without area penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the height of interconnects is increased to reduce resistance, then signal delay is improved, but capacitance increases significantly leading to higher power consumption
Solution Approach 1:
The patent applies local quality by implementing multi-height interconnect trenches where different regions of the interconnect layer have different trench depths. First trenches have a first depth while second trenches have a second depth that is greater than the first depth. This allows delay-critical signal paths to utilize taller interconnects for lower resistance, while non-critical paths use shorter interconnects to minimize capacitance and power consumption, thereby resolving the contradiction between signal delay and power consumption.
Solution Approach 2:
The patent segments the interconnect layer into multiple trench types with different depths. Instead of using a uniform interconnect height across the entire layer, the interconnect structure is divided into first trenches and second trenches with distinct depth characteristics. This segmentation enables independent optimization of resistance and capacitance for different signal paths, allowing the system to achieve low resistance where needed without globally increasing capacitance.
2Loss of time
If the width of interconnects is increased to decrease resistance, then signal delay is improved, but area increases resulting in area penalty
Solution Approach 1:
The patent resolves the contradiction between resistance and area by transitioning from width-based resistance reduction to height-based resistance reduction. Instead of increasing interconnect width to decrease resistance, the invention increases interconnect height by creating deeper trenches. This dimensional change allows resistance reduction without occupying additional lateral area, thereby improving signal delay without incurring area penalty.
3Ease of manufacture
If uniform interconnect heights are used across the layer, then manufacturing is simplified, but the ability to optimize resistance and capacitance independently is lost
Solution Approach 1:
The patent implements local quality by creating regions with different interconnect trench depths within the same interconnect layer. First trenches have a first depth suitable for standard signal paths, while second trenches have a greater second depth for delay-critical paths. This local differentiation maintains manufacturing feasibility through systematic trench formation processes while providing the adaptability to optimize resistance and capacitance independently for different signal requirements.
Data Source
AI summary
Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.