Multi-Height MUGFET Formation via Selective Etching
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Solution Overview
Problem
Existing integrated circuit structures face challenges in forming multiple-height FinFET and MUGFET structures with varying sidewall heights to optimize transistor performance and electrical isolation, as current methods lack the capability to simultaneously form different transistor shapes with precise control over etch characteristics and electrical properties.
Innovation Solution
A method involving the formation of trench isolation regions and hardmask layers to create silicon regions with different depths, allowing for the simultaneous etching of silicon fins to varying heights, which exposes a greater sidewall area and enables the formation of multiple-height FinFET, MUGFET, and tri-gate structures using damascene processing techniques, with the option to optimize etch characteristics and electrical isolation properties by selecting appropriate hardmask materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional methods are used to form transistor structures, then manufacturing simplicity is maintained, but the capability to form multiple-height structures with varying sidewall heights is lost
Solution Approach 1:
The patent segments the transistor formation process into distinct stages: forming shallow trench isolation regions, depositing multiple hardmask layers, patterning mandrels, and performing selective etching. Each stage prepares the structure for the next, enabling the final multi-height configuration through systematic division of the complex formation process
Solution Approach 2:
The patent performs preliminary actions by pre-forming shallow trench isolation regions to define silicon regions, depositing hardmask layers before mandrel formation, and patterning mandrels to predetermined depths. These preliminary structures serve as templates that guide subsequent etching operations to achieve the desired multiple-height transistor structures
2Shape
If uniform etching depth is used for all silicon regions, then manufacturing simplicity is maintained, but the ability to expose different sidewall areas is lost
Solution Approach 1:
The patent applies local quality by creating different etch conditions in different regions of the substrate. Hardmask layers are selectively removed from specific silicon regions, and mandrels are etched to different depths in different areas. This enables each silicon region to receive a tailored etch depth, exposing the desired sidewall area locally while maintaining overall process control
Solution Approach 2:
The patent transitions from two-dimensional planar transistors to three-dimensional multi-height structures by varying the etch depth dimension. Different silicon regions are etched to different depths, creating vertical height variations that expose different sidewall areas and enable multiple-height transistor configurations
3Adaptability or versatility
If all transistors are formed with the same height, then manufacturing simplicity is maintained, but performance optimization through adjusted sidewall areas is lost
Solution Approach 1:
The patent changes the etch depth parameter selectively across different silicon regions to optimize transistor performance. By controlling the etch depth, the exposed sidewall area is adjusted, which directly influences transistor characteristics such as drive current and threshold voltage. This parameter variation enables performance optimization while using the same base fabrication process
Data Source
AI summary
A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure and a second rectangular fin structure, both positioned on a substrate. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. A gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The gate conductor is positioned adjacent to a relatively larger portion of the sides of the second rectangular fin structure and is positioned adjacent to a relatively smaller portion of the sides of the first rectangular fin structure.