Multi-Height Standard Cells for IC Area Reduction
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Solution Overview
Problem
Existing integrated circuit designs using standard cells with fixed architectures limit design efficiency and area occupancy due to predetermined cell dimensions and routing constraints.
Innovation Solution
The integration of multi-height standard cells with selection transistors and efficient routing of gate lines and connection wirings, allowing for flexible cell heights and reduced area occupancy while enhancing performance by optimizing selection node placement and signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard cells with fixed architectures are used, then design simplicity is maintained, but area occupancy increases and design efficiency decreases
Solution Approach 1:
The standard cell is divided into multiple regions (first region between first and second power rails, second region between second and third power rails) with different functional blocks. Each region can be independently configured with selection transistors and gate lines, allowing flexible area utilization while maintaining overall cell functionality.
Solution Approach 2:
The patent introduces multi-height standard cells that extend in the vertical direction (second direction perpendicular to power rail extension). By utilizing multiple power rails (first, second, third power rails) stacked vertically, the design achieves three-dimensional space utilization, reducing horizontal area occupancy while increasing vertical dimension usage.
2Productivity
If standard cells with fixed architectures are used, then manufacturing simplicity is maintained, but design efficiency decreases
Solution Approach 1:
The standard cell design incorporates universal selection transistors (first through eighth selection transistors) and common gate lines (first, second, third selection gate lines) that can serve multiple functional blocks within the same cell. This multi-functional approach allows a single cell architecture to handle various logic operations, improving design efficiency without proportionally increasing complexity.
Solution Approach 2:
Multiple selection transistors are merged into a unified structure controlled by shared gate lines. The first selection gate line controls both second and sixth selection transistors, while the third selection gate line controls both third and seventh selection transistors. This merging reduces the number of independent control signals needed, improving design efficiency while managing complexity.
3Area of stationary object
If selection transistors and gate lines are integrated, then area occupancy is reduced, but routing complexity increases
Solution Approach 1:
Selection transistors are strategically placed in specific regions (first region and second region) with tailored configurations. The first selection transistor pulls up the first output node, while the second selection transistor pulls down the first output node. This localized optimization allows area reduction in critical regions without requiring complex routing throughout the entire cell.
Solution Approach 2:
The row connection wiring connects the first selection gate line and the third selection gate line, creating equipotential regions for complementary transistor pairs. This equalization simplifies the voltage distribution and reduces routing complexity by providing symmetric voltage references for pull-up and pull-down transistor control.
Data Source
AI summary
An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.