Multi-Height Switch Cell Layout With Alternating Back-Side Power Rails
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Solution Overview
Problem
Conventional semiconductor devices face challenges with long contacts connecting global power rails to multi-height switch cells, leading to increased risk of shorts and high capacitance, which affect performance.
Innovation Solution
The semiconductor device incorporates a multi-height switch cell with alternating global and local back-side power rails, using shorter contacts to connect to transistors, reducing the risk of shorts and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long contacts are used to connect global power rails to multi-height switch cells, then power distribution is achieved, but the risk of electrical shorts increases and capacitance becomes high
Solution Approach 1:
The invention divides the single long contact connection into multiple shorter contact segments by introducing intermediate local power rails. Instead of one continuous long contact from the global power rail to the switch cell, the power distribution path is segmented into multiple shorter contacts through local power rails positioned at different heights, thereby reducing the length of each individual contact and minimizing short circuit risk.
Solution Approach 2:
The invention transitions from a two-dimensional planar contact layout to a three-dimensional vertical arrangement by utilizing multiple power rail heights. Local power rails are positioned at different vertical levels (e.g., first through fourth power rail levels) to create staggered contact points, effectively using the vertical dimension to reduce horizontal contact length and associated capacitance.
2Productivity
If long contacts are used to connect global power rails to multi-height switch cells, then power distribution is achieved, but capacitance becomes high affecting performance
Solution Approach 1:
The power distribution path is segmented into multiple shorter contact segments through intermediate local power rails. This segmentation reduces the total capacitance by breaking up the long continuous contact into shorter segments, each with lower individual capacitance, thereby improving device performance and reducing energy consumption.
Solution Approach 2:
By utilizing vertical stacking of power rails at different heights, the invention reduces the horizontal span of contacts. This dimensional transition creates shorter contact paths that exhibit lower capacitance values, directly addressing the performance and energy consumption issues associated with long contacts.
3Ease of manufacture
If long contacts are used for power rail connections, then electrical connectivity is established, but patterning difficulty increases
Solution Approach 1:
The manufacturing process is simplified by segmenting the contact patterning into multiple smaller, more manageable steps. Instead of patterning one long contact, the process divides it into several shorter contact segments corresponding to different power rail levels, making each patterning operation easier to execute with standard fabrication techniques.
Solution Approach 2:
The invention leverages the vertical dimension to create a multi-level contact structure that is easier to pattern. By distributing contacts across different vertical levels rather than requiring one long horizontal contact, the patterning process becomes more compatible with standard semiconductor manufacturing capabilities.
Data Source
Figure 1A
Figure 1B~1C
Figure 1D
AI summary
Semiconductor devices are provided. A semiconductor device includes: a first stacked field-effect transistor, FET; a second stacked FET adjacent the first stacked FET; a first global back-side power rail between, and electrically connected to, the first stacked FET and the second stacked FET; a third stacked FET adjacent the second stacked FET; a local back-side power rail between, and electrically connected to, the second stacked FET and the third stacked FET; a fourth stacked FET adjacent the third stacked FET; and a second global back-side power rail between, and electrically connected to, the third stacked FET and the fourth stacked FET.