Multi-Hit Fault Attack Simulation for Circuit Security Verification
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Solution Overview
Problem
Existing circuit design verification methods fail to effectively simulate and identify vulnerabilities to fault attacks, such as laser, electromagnetic, and voltage glitches, which can compromise security-critical functions, necessitating a more targeted and efficient simulation approach.
Innovation Solution
A fault attack simulation model is employed to generate and simulate multi-hit attacks with defined characteristics, such as number of hits, time window, and targeted circuit elements, using hardware simulators to evaluate potential vulnerabilities and output simulation results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional verification methods are used, then development time can be reduced by performing functional verification early, but the ability to identify vulnerabilities to fault attacks is insufficient
Solution Approach 1:
The patent applies preliminary action by performing fault attack simulation during the logical design phase before physical implementation. The system automatically generates fault attack scenarios and executes them on the logical design using hardware simulators, enabling security verification to be conducted in advance rather than after deployment, thus resolving the contradiction between improving security verification capability and maintaining development time efficiency
2Reliability
If comprehensive fault attack simulation is performed on all circuit elements, then verification thoroughness is improved, but simulation time and computational resources increase significantly
Solution Approach 1:
The patent applies local quality by focusing fault attack simulation on specific target circuit elements identified through vulnerability analysis rather than uniformly testing all elements. The system determines which circuit elements are most susceptible to fault attacks based on their functionality and position in the logical design, thereby concentrating verification resources on critical areas and reducing overall simulation time while maintaining thoroughness where it matters most
3Extent of automation
If manual fault attack simulation is performed, then control over simulation parameters is improved, but automation level and verification efficiency deteriorate
Solution Approach 1:
The patent applies self-service by implementing an automated verification system that independently generates fault attack scenarios, selects target circuit elements, executes simulations, and analyzes results without requiring extensive manual intervention. The system uses vulnerability analysis to automatically determine simulation parameters and target elements, while still allowing users to configure high-level verification goals and constraints, thus achieving high automation while preserving necessary control flexibility
Data Source
AI summary
A method, system and apparatus for fault attack simulation. A circuit design and a fault attack simulation model defining characteristic of a multi-hit attack to be simulated in the circuit are obtained. The fault attack simulation model defines at least: a number of hits during the multi-hit attack, a time window in which the multi-hit attack is simulated, and a list of potentially attacked circuit elements of the circuit during the multi-hit attack. Based on the fault attack simulation model, a plurality of fault attacks adhering to the fault attack simulation are generated. Each generated fault attack includes a plurality of hits occurring during the time window and with respect to the list of potentially attacked circuit elements. The generated fault attacks are simulated using a hardware simulator that simulates the design of the circuit. The results of the simulation are outputted to the user.