Deterministic Data Interleaving for Multi-Host Single-Port Memory Access
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Solution Overview
Problem
Existing technologies face challenges in efficiently managing and processing commands from multiple hosts via a single port of a device, leading to inefficiencies in link efficiency, memory overhead, and processing latency.
Innovation Solution
The implementation of processing circuitry that segments commands from multiple hosts into segments of a predetermined size, which are then transmitted to respective data structures corresponding to the host ID, allowing for interleaved data transfers to improve fairness and link efficiency, while using an interposer to couple multiple hosts to a single port.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple hosts are coupled to a single port of a device, then the device can serve multiple hosts, but link efficiency deteriorates due to command processing bottlenecks
Solution Approach 1:
The patent segments incoming commands from multiple hosts into individual command segments and distributes them to separate queues associated with each host. This segmentation allows parallel processing of commands from different hosts, preventing bottlenecks and improving link efficiency while maintaining the ability to serve multiple hosts through a single physical port.
2Device complexity
If commands from multiple hosts are processed sequentially through a single port, then processing is simplified, but access fairness to memory deteriorates
Solution Approach 1:
The patent implements dynamic queue management where commands from different hosts are placed in separate queues and processed in an interleaved manner. The processing circuitry dynamically selects which host's command to process next based on queue status, ensuring fair access to memory resources while maintaining manageable processing complexity through structured queue organization.
3Adaptability or versatility
If an interposer is used to couple multiple hosts to a single port, then host connectivity is improved, but memory overhead and processing latency increase
Solution Approach 1:
The interposer performs preliminary actions by pre-segmenting and pre-queuing commands from multiple hosts before they reach the device. This preliminary organization of commands into host-specific queues reduces the processing burden on the device, minimizing additional latency introduced by the interposer while maintaining improved host connectivity.
Data Source
AI summary
A device and related method, the device including a port, memory circuitry, and processing circuitry which is coupled to the port and to the memory circuitry. The processing circuitry receives multiple commands through the port, wherein the multiple commands are from at least two hosts using an interposer and wherein each command of the multiple commands includes a respective memory address and a respective port identification (ID). The processing circuitry segments each of the received commands into multiple segments, each segment being of a predetermined transfer size. The processing circuitry also transmits each segment of each command to a respective data structure instantiation corresponding to the port ID of the respective received command and performs data transfer for each segment of the multiple segments by accessing the memory circuitry at each respective memory address associated with each segment.