Multi-Host DMA System with Programmable Switches
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Solution Overview
Problem
In computing systems, managing direct memory access (DMA) engines consumes significant CPU resources, particularly in environments with multiple processors or virtual machines, hindering system performance.
Innovation Solution
A DMA system that supports multiple host processors by using a memory to store host profiles and interfaces, allowing data engines to be independently configured for different DMA operations across various interfaces, enabling other processors to manage DMA operations and freeing up CPU resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single host processor manages the DMA engine, then the DMA operations can be performed, but the CPU resources are significantly consumed, hindering system performance
Solution Approach 1:
The patent segments the DMA management functionality by introducing multiple data engines (first data engine, second data engine) that can be independently configured and managed by different host processors. This segmentation allows the workload to be distributed across multiple processors, reducing the burden on any single CPU and improving overall system performance while maintaining efficient DMA operations.
2Productivity
If multiple host processors are supported, then DMA operations can be distributed and CPU resources freed, but the device complexity increases
Solution Approach 1:
The patent implements universality by designing data engines that can serve multiple host processors through a common interface. The data engines are configured to support both single-host and multi-host operations, allowing the same hardware structure to adapt to different operational modes. This multi-functionality reduces the need for separate dedicated structures for each host processor, thereby limiting the increase in device complexity while still enabling distributed DMA management.
3Ease of operation
If DMA operations are centralized on one processor, then the system is simpler to manage, but the CPU resources are consumed and performance is hindered
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a unified interface that mediates between multiple host processors and the data engines. This intermediary layer allows different processors to manage DMA operations independently while maintaining a consistent and simple management paradigm. The interface abstracts the complexity of multi-processor coordination, preserving ease of operation while enabling distributed management that improves system performance.
Data Source
AI summary
A system can include a plurality of processors. Each processor of the plurality of processors can be configured to execute program code. The system can include a direct memory access system configured for multi-processor operation. The direct memory access system can include a plurality of data engines coupled to a plurality of interfaces via a plurality of switches. The plurality of switches can be programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles corresponding to the plurality of processors.