Multi-host Interface Controller with Integrated USB PHY and Analog Functions

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Solution Overview

Problem

Conventional memory devices face challenges in efficiently integrating multiple interfaces and managing heat dissipation, leading to increased manufacturing costs and potential signal interference, especially when incorporating USB functionality.

Innovation Solution

The solution involves separating the USB PHY and analog circuitry from the controller and memory array onto different IC dies, using multi-chip packaging and wire bonding, allowing for independent modification and improved thermal performance, while utilizing the 12 signal UTMI+Low Pin Count interface to support multiple operation modes with minimal additional signal pins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If USB PHY and analog circuitry are integrated into the controller IC die, then device functionality is improved, but heat dissipation increases and signal interference occurs

Engineering Contradiction:
Improvedevice functionalityVSAvoidheat dissipation and signal interference
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the memory device into separate IC dies: one die contains the controller and USB PHY, while another die contains the memory array. This segmentation allows the USB PHY to be isolated from the memory array, reducing signal interference and heat dissipation issues while maintaining full USB functionality.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If multiple interfaces are integrated into a single controller IC, then interface versatility is improved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improveinterface versatilityVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The controller IC die is designed with a universal interface architecture that can support multiple interface types (USB, SD, MMC, etc.) through a single multi-functional interface block. This allows the controller to communicate with different host devices using different protocols without requiring separate dedicated hardware for each interface type, thereby reducing manufacturing complexity while maintaining versatility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If USB PHY is integrated with the controller, then device capability is improved, but manufacturing cost increases in high volume settings

Engineering Contradiction:
Improvedevice capabilityVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

By segmenting the USB PHY into a separate IC die that can be independently manufactured and then packaged with the controller die, the patent enables specialized high-volume production of each component. This approach allows manufacturers to optimize the fabrication process for each die type separately and benefit from economies of scale, ultimately reducing per-unit manufacturing costs compared to producing a single integrated chip containing all functions.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7898091B2Multi-host interface controller with USB PHY/analog functions integrated in a single package
Publication Date: 2011.03.01 SANDISK TECHNOLOGIES LLC
  • US7898091B2 patent drawing
  • US7898091B2 patent drawing

AI summary

In a first embodiment, an apparatus and a method of fabrication thereof includes a substrate, a controller formed on a first integrated circuit (IC) die and disposed on the substrate, a second IC die embodying circuitry configured to enable communication between the controller and an external device, first I/O pads disposed on the first IC die, second I/O pads disposed on the second IC die, wire bonding interconnections coupling at least one of the first I/O pads with at least one of the second I/O pads, and a memory array formed on a third IC die and configured to enable communication with the controller. In a second embodiment the memory array is alternatively integrated into the first IC die.