Multi-Input A/D Converter Circuit Using Time-Multiplexed Buffer

The patent merges multiple buffer functions into a single shared buffer by introducing selector switches. Instead of having separate buffers for each of the 256 input signals, one buffer is shared among all inputs, with selector switches routing the appropriate input signal to the buffer. This reduces the number of buffers from 256 to 1, dramatically reducing layout area and current consumption while maintaining conversion accuracy through proper signal routing and timing control.

The single buffer serves multiple functions by processing different input signals at different time periods. The buffer is universally used for impedance transformation and circuit separation for all 256 input channels, with the selector switches directing each input signal to the same buffer in sequence. This multi-functional approach eliminates the need for dedicated buffers for each channel while preserving the necessary signal processing quality.

Multiple buffer instances are merged into a single buffer that is time-multiplexed across all input channels. The selector switches route different input signals to the same buffer at different times, allowing one buffer to provide drive capacity for all 256 inputs sequentially. This eliminates the need for 256 separate buffers, reducing current consumption and layout area while maintaining adequate drive capacity through proper timing control.

The buffer operates periodically, processing one input signal at a time in a sequential manner. During each time period, the selector switch connects one specific input signal to the buffer, which then processes and outputs the signal. This periodic operation allows a single buffer to serve multiple channels over time, reducing the total number of buffers needed while maintaining the required drive capacity for each individual channel when it is active.

The system performs preliminary sampling and holding of input signals in capacitors before the buffer processes them. During the sampling phase, each input signal is captured and stored in its corresponding sampling capacitor. Then, during the conversion phase, the selector switch connects the appropriate held signal to the buffer, which processes it without needing to charge from scratch. This preliminary action allows small-capacity buffers to achieve fast response times because they are processing pre-charged signals rather than charging during the conversion process.

The conversion process is segmented into distinct phases: sampling phase where signals are captured in capacitors, and conversion phase where the buffer processes the held signals. This temporal segmentation allows the buffer to operate at full capacity during the conversion phase without being constrained by the need to simultaneously charge multiple signals. The sampling capacitors act as intermediate storage, decoupling the sampling operation from the conversion operation, thereby enabling fast response with small buffers.

The system uses periodic time-multiplexed switching where the selector switch sequentially connects different input signals to the single buffer in rapid succession. Each input signal is processed during its allocated time slot, and the buffer output is accordingly switched to the ADC. This periodic switching approach maintains relatively simple circuitry (one buffer, one ADC, one selector switch) while achieving fast overall conversion by efficiently utilizing time slots. The key is that the switching occurs so rapidly that the total conversion time remains short despite the sequential nature of processing multiple channels.

The system dynamically allocates time slots for processing different input channels based on the sampling rate and number of channels. The selector switch and buffer operation are dynamically controlled to process each of the 256 inputs within a defined time period, adjusting the switching frequency and duty cycle to optimize the balance between circuit simplicity and conversion speed. This dynamic time-division multiplexing allows the simple sequential architecture to achieve high-speed conversion by optimizing the timing parameters.