Multi-Input Floating-Point Adder With Unified Sticky-Bit Rounding
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Solution Overview
Problem
Existing floating-point addition methods for multiple operands require multiple iterations and consume significant chip space when using multiple two-input adders, leading to inefficiencies in power consumption and chip space utilization.
Innovation Solution
A multi-input adder design that aligns mantissa bits of operands based on exponents, calculates a sticky bit value to minimize rounding errors, and performs normalization and rounding in a single operation, reducing the need for multiple iterations and hardware resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple two-input adders are used to perform parallel addition of multiple floating-point numbers, then addition speed is improved, but chip space consumption increases significantly
Solution Approach 1:
The patent merges multiple two-input adder operations into a single multi-input adder that can process three or more floating-point operands simultaneously. This consolidation integrates the alignment, addition, and normalization functions for multiple operands into one unified hardware structure, reducing the total chip space required while maintaining parallel processing capability.
Solution Approach 2:
The multi-input adder is designed as a universal component that can handle addition of any number of floating-point operands (three or more) in a single operation. This multi-functional design eliminates the need for multiple specialized two-input adders, achieving both space efficiency and computational versatility.
2Productivity
If multiple two-input adders are used to perform parallel addition, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple addition operations into a single multi-input adder structure that processes three or more operands simultaneously. This merging approach maintains high productivity by performing parallel-like operations in one unified device, while reducing overall system complexity by eliminating the need to coordinate multiple separate adders.
3Area of stationary object
If multiple addition operations are performed sequentially using a single adder, then chip space is optimized, but power consumption increases due to multiple iterations
Solution Approach 1:
The multi-input adder merges multiple addition operations into a single computational pass, processing three or more floating-point numbers simultaneously. This eliminates the need for sequential iterations, reducing power consumption by avoiding repeated activation of alignment, addition, and normalization logic while maintaining compact chip space usage.
Data Source
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AI summary
Methods, systems, and apparatus, including an apparatus for adding three or more floating-point numbers. In one aspect, a method includes receiving, for each of three or more operands, a set of bits that include a floating-point representation of the operand. For each other operand, the mantissa bits of the operand are shifted such that the bits of the operand align with the bits of a given operand. A sticky bit for each other operand is determined. An overall sticky bit value is determined based on each sticky bit. The overall sticky bit value is zero whenever all of the sticky bits are zero or at least two sticky bits are non-zero and do not match. The overall sticky bit value matches the value of each non-zero sticky bit whenever all of the non-zero sticky bits match or there is only one non-zero sticky bit.