Multi-Input Serial Adder Logic Tree for FPGA Routing Congestion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Field programmable gate arrays (FPGAs) are inefficient in implementing fundamental logic units like serial adders, leading to underutilization of logic and overwhelming routing due to the number of nets required for circuit implementation.
Innovation Solution
A functional unit in a logic circuit that can accumulate more than two serial inputs and provide one serial summation output, implemented as a logical tree within a processing unit of an FPGA, utilizing a plurality of full adder circuits with a carried state maintained among them, allowing for efficient construction of mathematical functions such as matrix multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a serial adder with two primary inputs is implemented in an FPGA, then the addition function can be achieved, but the entire 6-input lookup table (LUT) is consumed, leading to logic underutilization
Solution Approach 1:
The patent combines multiple input signals (more than two) into a single serial adder unit, allowing the same LUT resource to perform multiple functions across different clock cycles. By merging the functionality of multiple adders into one time-multiplexed unit, the design achieves better logic utilization without increasing LUT consumption.
Solution Approach 2:
The patent introduces dynamic time-multiplexing where the adder unit changes its input connections based on the current operation phase. The same physical adder circuit dynamically switches between different input pairs across clock cycles, enabling versatile mathematical operations (addition, subtraction, multiplication) with a fixed hardware structure, thereby improving adaptability without proportionally increasing device complexity.
2Productivity
If a serial adder with two primary inputs is implemented in an FPGA, then the addition function can be achieved, but the routing is overwhelmed by the number of nets required for circuit implementation
Solution Approach 1:
The patent designs a universal adder unit that can perform multiple mathematical operations (addition, subtraction, multiplication) by reusing the same hardware resources across different clock cycles. This multi-functionality reduces the need for separate dedicated circuits for each operation, thereby reducing the total number of nets and routing congestion while maintaining high productivity in constructing various mathematical functions.
Solution Approach 2:
The patent segments mathematical operations into discrete clock cycle stages, where different input pairs are processed in sequence through the same adder unit. By dividing the computational task into time-separated segments rather than requiring simultaneous processing, the design reduces the number of interconnect nets needed at any given moment, alleviating routing congestion.
Data Source
AI summary
Implementations for a functional unit are provided, wherein the functional unit can accumulate more than two serial inputs and provide one serial summation output. The serial inputs and outputs can be single bits or multiple bit busses. The functional unit can be implemented as a logical tree, where any two points are connected by one path. The functional unit can be incorporated into a processing unit of a programmable device to allow for construction of various functions.