Multi-interface Bus Protocol Adaptation Logic

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Solution Overview

Problem

Implementing a multi-interface high-speed bus that can accommodate both source synchronous and asynchronous bus operations is challenging, especially in high-bandwidth applications, due to issues like signal skew introduced by quick switches and multiplexers.

Innovation Solution

A system that includes a network device with circuit boards capable of communicating using either synchronous or asynchronous bus protocols, featuring a multiplexer to select between clock signals and logic for data recovery based on the type of external circuit board, allowing for dynamic configuration of bus operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If quick switches and multiplexers are used to switch between synchronous and asynchronous buses, then multi-interface compatibility is achieved, but signal skew is introduced

Engineering Contradiction:

Improvemulti-interface compatibilityVSAvoidsignal timing accuracy

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The system segments the bus interface into separate synchronous and asynchronous communication paths, each optimized for its specific protocol. The fabric card contains dedicated logic for handling synchronous packets with explicit timing and asynchronous packets with implicit timing, avoiding the need for switching between modes and eliminating signal skew issues.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The fabric card is designed with universal functionality to handle both synchronous and asynchronous bus protocols simultaneously through a single interface. The communication logic can process packets from either bus type without requiring physical switching or mode changes, achieving multi-interface compatibility without the harmful effects of quick switches.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If a common clock is used for source synchronous bus operation, then signal timing is simplified, but asynchronous communication is not supported

Engineering Contradiction:

Improvecommunication speedVSAvoidbus protocol compatibility

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The system dynamically adapts its communication mode based on the packet type received. When a synchronous packet is detected, the fabric card uses explicit timing signals and common clock references for high-speed operation. When an asynchronous packet is detected, it switches to implicit timing with locally generated clocks, maintaining adaptability across different bus protocols while preserving optimal performance for each mode.

Inventive Principle:

Principle #15Dynamics

3Reliability

If separate physical connections are provided for synchronous and asynchronous buses, then signal integrity is maintained, but device complexity increases

Engineering Contradiction:

Improvesignal integrityVSAvoidnumber of connection paths

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The fabric card acts as an intermediary that receives both synchronous and asynchronous packets through a single shared physical interface. It contains internal logic that identifies packet types and routes them to appropriate processing paths, eliminating the need for separate physical connections while maintaining signal integrity through protocol-specific handling within the card's logic.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8411695B1Multi-interface compatible bus over a common physical connection

Publication Date: 2013.04.02 JUNIPER NETWORKS INC

AI summary

A multi-interface bus allows for different bus standards to be implemented over the same set of physical bus lines. More particularly, in one implementation, the system includes a first circuit board, a second circuit board, and a bus connecting the first and second circuit boards. The second circuit board is configured to communicate with the first circuit board using either a synchronous or an asynchronous bus protocol determined based on a bus protocol used by the first circuit board.