Multi-Interface MBIST Circuit for Shared Memory Test Routing
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Solution Overview
Problem
Conventional semiconductor memory devices lack the capability to efficiently test multiple memory types and interfaces, leading to limited customization and increased footprint due to separately targeted MBIST circuits and complex signal routing.
Innovation Solution
A multi-interface test mechanism incorporating a test circuit and interface manager that supports diagnostics for various memory types, including DRAM, SRAM, and NAND, within a single common test circuit, reducing footprint and simplifying signal routing by using a shared path and customizable testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separately targeted MBIST circuits are used for different memory types, then testing capability for specific memory types is improved, but device footprint and circuit complexity increase
Solution Approach 1:
The patent implements a universal MBIST circuit that can test multiple memory types (DRAM, SRAM, NAND) through a single integrated test interface. The circuit includes configurable test pattern generators and comparators that can be programmed to accommodate different memory architectures and interface protocols, eliminating the need for separate dedicated test circuits for each memory type.
Solution Approach 2:
The MBIST circuit incorporates dynamic configuration capabilities through interface managers that can adapt the test circuit's behavior based on the target memory type. Control logic dynamically reconfigures test patterns, timing parameters, and interface protocols to match the specific requirements of DRAM, SRAM, or NAND memory being tested, allowing one circuit to serve multiple functions.
2Measurement precision
If multiple dedicated test circuits are implemented for different memory types, then test precision for each memory type is improved, but device complexity and signal routing complexity increase
Solution Approach 1:
The patent merges multiple dedicated test circuits into a single integrated MBIST unit with shared test pattern generators, comparators, and control logic. The unified circuit architecture consolidates previously separate test paths into common signal routes, reducing the overall complexity of signal routing while maintaining the ability to precisely test different memory types through software-configurable parameters.
3Adaptability or versatility
If customized test circuits are used for each memory type, then adaptability to specific memory interfaces is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent implements a universal test circuit architecture with programmable interface managers that can be manufactured as a single standard cell design. The circuit includes configurable components such as parameterizable test pattern generators and protocol adapters that can be programmed via HDL code to support different memory interfaces (DRAM, SRAM, NAND), allowing customization through software rather than hardware changes, thereby simplifying manufacturing.
Data Source
AI summary
Methods, apparatuses, and systems related to adjustment of circuit tests are described. A memory device may include a self-test circuit that is configured to selectively suspend collection and/or processing of test results for one or more portions of the self-test.