Multi-Interposer Bridge Layout for Stress-Limited Die Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor integrated circuits shrink, connecting multiple functional dies through interposers becomes increasingly challenging due to issues such as stress and stitching problems associated with large interposers, which affect reliability and fabrication efficiency in chip-on-wafer-on-substrate systems.
Innovation Solution
The use of bridge components on a molded platform to partition and connect multiple chip-on-wafer structures, integrating multiple interposers to form a smaller, more reliable platform, thereby reducing stress and avoiding stitching issues by using multiple smaller interposers and encapsulating them with suitable materials for protection and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single large interposer is used to connect multiple functional dies, then connectivity between dies is achieved, but stress and stitching problems increase reducing reliability
Solution Approach 1:
The patent divides a single large interposer into multiple smaller interposers (first interposer and second interposer). Each interposer connects to a subset of functional dies, thereby segmenting the stress and eliminating stitching problems associated with large single interposers. This segmentation maintains die connectivity while improving overall device reliability.
2Reliability
If multiple smaller interposers are used to reduce stress, then reliability improves, but device complexity increases
Solution Approach 1:
The substrate acts as an intermediary that connects multiple interposers (first interposer and second interposer). Each interposer is independently configured on the substrate, simplifying individual interposer design while the substrate provides the integration framework. This mediator approach reduces overall system complexity compared to designing a single complex large interposer.
3Adaptability or versatility
If multiple chip-on-wafer structures are integrated, then functionality increases, but fabrication complexity increases
Solution Approach 1:
The fabrication process is segmented into independent stages for each interposer-die assembly. Each interposer can be fabricated and tested independently before final integration on the substrate, allowing parallel processing and simplifying the overall fabrication workflow despite multiple functional integrations.
Solution Approach 2:
Interposers and their attached functional dies are prepared and pre-assembled before final substrate integration. This preliminary action allows independent optimization and testing of each module, reducing fabrication complexity during final assembly while maintaining high functional integration capability.
Data Source
AI summary
Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.