Multi-Interposer Layout for Shorter Die Pathways in 3D Packaging
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Solution Overview
Problem
Three-dimensional semiconductor devices face challenges with increased ohmic losses and RC delays due to long electrical pathways and the complexity of using a single large interposer for multiple semiconductor device dies, which can lead to reduced integration density and increased packaging complexity.
Innovation Solution
Employing two separate interposers for different semiconductor device dies, such as a serializer/de-serializer device die and other dies like SoC or HBM, allows for reduced electrical pathway lengths and avoids the complexity of a single large interposer, thereby minimizing ohmic losses and RC delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single large interposer is used for multiple semiconductor device dies, then integration density can be achieved, but ohmic losses and RC delays increase due to long electrical pathways
Solution Approach 1:
The patent divides a single large interposer into multiple smaller interposers, each supporting specific semiconductor device dies. This segmentation reduces the electrical pathway lengths within each interposer, thereby decreasing ohmic losses and RC delays while maintaining overall integration density through the stacked three-dimensional arrangement of multiple interposer-die assemblies.
2Adaptability or versatility
If a single large interposer is used for multiple semiconductor device dies, then all dies can be supported on one substrate, but packaging complexity increases
Solution Approach 1:
The patent segments the packaging structure into multiple independent interposer-die assemblies that are stacked vertically. Each interposer is smaller and manages fewer dies, simplifying the packaging process for each unit while the three-dimensional stacking provides the versatility to support multiple different semiconductor device dies in an integrated system.
3Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking of multiple interposer-die assemblies. This dimensional change allows integration density to be increased by utilizing the vertical space rather than continuously reducing minimum feature sizes, thereby avoiding the escalating manufacturing precision requirements associated with smaller features.
Data Source
AI summary
Various disclosed embodiments include a substrate, a first interposer coupled to the substrate and to a first semiconductor device die, and a second interposer coupled to the substrate and to a second semiconductor device die. The first semiconductor device die may be a serializer/de-serializer die and the first semiconductor device die coupled to the first interposer may be located proximate to a sidewall of the substrate. In certain embodiments, the second semiconductor device die may be a system-on-chip die. In further embodiments, the second interposer may also be coupled to high bandwidth memory die. Placing a serializer/de-serializer die proximate to a sidewall of a substrate allows a length of electrical pathways to be reduced, thus reducing impedance and RC delay. The use of smaller, separate, interposers also reduces complexity of fabrication of interposers and similarly lowers impedance associated with redistribution interconnect structures associated with the interposers.