Multi-Interposer Semiconductor Package for Signal Noise Isolation

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Solution Overview

Problem

Current semiconductor packages with multiple interposers face challenges in optimizing signal path density and noise coupling, leading to performance degradation due to the need for high-speed and low-speed signal paths to coexist, which results in noise interference and reduced overall performance.

Innovation Solution

The implementation of a semiconductor package design featuring separate interposers with distinct signal path densities, where a first interposer with a higher number of 'fast signal paths' and a second interposer with fewer 'slow signal paths' are physically separated to reduce noise coupling, allowing high-speed and low-speed communications to occur without interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple interposers with both fast and slow signal paths are integrated in a single semiconductor package, then signal path density and integration are improved, but noise coupling increases and performance deteriorates

Engineering Contradiction:
Improvesignal path densityVSAvoidnoise coupling
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the interposer structure into multiple separate interposers, where each interposer is dedicated to specific signal path types (fast or slow). This segmentation physically separates the signal paths that would otherwise be coupled, thereby reducing noise interference while maintaining high signal path density within each individual interposer.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If high-speed and low-speed signal paths coexist in the same interposer, then device complexity is reduced, but signal interference increases and communication reliability decreases

Engineering Contradiction:
Improveinterposer structureVSAvoidcommunication reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the interposer functionality across multiple separate interposers, with each interposer optimized for specific signal speed requirements. This segmentation eliminates cross-speed signal interference, thereby improving communication reliability while keeping the overall system complexity manageable through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts slow signal paths from the fast signal path interposer and places them on separate dedicated interposers. This extraction removes the source of noise coupling and interference, allowing high-speed signals to operate without contamination from lower-speed signal transitions.

Inventive Principle:
Principle #2Taking out (Extraction)

3Object-affected harmful factors

If separate interposers with distinct signal path densities are used, then noise coupling is reduced, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvenoise couplingVSAvoidinterposer configuration
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent segments the package into multiple interposers with optimized signal path densities for their specific functions. While this increases the number of components, each interposer can be manufactured and tested independently, simplifying the overall manufacturing process and quality control despite the increased device complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240014113A1Semiconductor package including interposors and electronic system
Publication Date: 2024.01.11 SAMSUNG ELECTRONICS CO LTD
  • US20240014113A1 patent drawing
  • US20240014113A1 patent drawing
  • US20240014113A1 patent drawing

AI summary

An electronic system includes a first interposer including first signal paths, a second interposer spaced apart from the first interposer and including second signal paths, a first semiconductor chip structure on the first and second interposers and including a first circuit region and a second circuit region, and a second semiconductor chip structure on the first and second interposers and spaced apart from the first semiconductor chip structure. The second semiconductor chip structure includes a third circuit region configured to communicate with the first circuit region of the first semiconductor chip structure at a first rate through the first signal paths of the first interposer and a fourth circuit region configured to communicate with the second circuit region of the first semiconductor chip structure at a second rate, different from the first rate, through the second signal paths of the second interposer.