Multi-Interposer Semiconductor Package with Vertical Through Electrodes
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Solution Overview
Problem
The challenge in achieving multi-functionality and high integration in semiconductor packages is limited by the restricted number of wiring lines that can be formed on the surface of an interposer, leading to difficulties in signal transfer between system and memory chips, and increased manufacturing costs due to the need for precise wiring processes and larger interposer sizes.
Innovation Solution
A semiconductor package design that includes multiple interposers and semiconductor chips, with through electrodes connected via wiring lines and vias, allowing for increased signal transfer capabilities and integration, while maintaining a compact form factor through the use of additional interposers and conductive connection members.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of the interposer is increased to enlarge the area for forming wiring lines, then the number of wiring lines for signal transfer can be increased, but warping may occur
Solution Approach 1:
The interposer is divided into multiple segments (first interposer and second interposer) that are connected through vias and wiring lines. This segmentation allows the total wiring capacity to be distributed across multiple smaller units, achieving high integration without requiring a single large interposer that would warp.
2Quantity of substance
If wiring lines are thinly formed to increase the number of wiring lines in a unit area, then the number of wiring lines can be increased, but a precise wiring process is required which increases manufacturing cost
Solution Approach 1:
The patent transitions from planar wiring (2D) to three-dimensional wiring by forming wiring lines and vias that extend through the thickness of the interposer. This vertical dimension allows additional wiring paths without reducing the thickness of individual wiring lines, thereby maintaining manufacturing feasibility while increasing total wiring capacity.
3Adaptability or versatility
If the number of inputs/outputs of the system chip and memory chip is increased to achieve multi-functionality and high integration, then the signal transfer capability is improved, but the number of wiring lines required exceeds the limitation of what can be formed on the interposer surface
Solution Approach 1:
The patent implements a nested structure where the second interposer is positioned over the first interposer, with wiring lines and vias extending between them. This nested arrangement effectively multiplies the wiring capacity by stacking functional layers vertically, enabling high integration and multi-functionality without being constrained by the surface area of a single interposer layer.
Data Source
AI summary
A semiconductor package includes a first interposer; first and second semiconductor chips horizontally mounted over the first interposer and electrically connected with the first interposer; and a second interposer disposed over the first and second semiconductor chips and electrically connected with the first and second semiconductor chips, wherein the first semiconductor chip includes a plurality of first through electrodes, and the second semiconductor chip includes a plurality of second through electrodes, and wherein the first through electrodes of the first semiconductor chip and the second through electrodes of the second semiconductor chip are electrically connected with each other through the first and second interposers.