Multi-Interposer Semiconductor Package for Warpage Control
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Solution Overview
Problem
Current semiconductor packages face challenges in efficiently connecting multiple semiconductor chips due to warpage issues caused by thermal expansion mismatches, leading to reliability concerns and increased design and manufacturing complexities.
Innovation Solution
The semiconductor package employs small interposers with different functions to connect semiconductor chips to the package substrate and each other, using through-electrodes and conductive connection structures, while a molding layer surrounds the chips and interposers to manage warpage and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are mounted on a package substrate, then the functionality and capacity of the electronic device are improved, but warpage occurs due to thermal expansion mismatches
Solution Approach 1:
The patent divides the package substrate into multiple regions, each containing specific semiconductor chips and interposers. The segmentation allows different areas to have optimized thermal and mechanical properties, reducing overall warpage while maintaining multiple functionalities.
Solution Approach 2:
Interposers are introduced as intermediary components between the semiconductor chips and the package substrate. These interposers act as mediators that compensate for thermal expansion mismatches and reduce warpage, enabling stable mounting of multiple diverse chips.
2Reliability
If interposers are used to connect semiconductor chips, then electrical connection reliability is improved, but device complexity increases
Solution Approach 1:
The interposers are designed with multi-functionality, serving both as electrical connection structures (through-electrodes, conductive connections) and as mechanical support elements that reduce warpage. This universal design improves reliability without proportionally increasing complexity.
Solution Approach 2:
Different interposers are designed with specific local qualities tailored to their positions and functions. For example, interposers near chips with higher thermal expansion coefficients have optimized properties to compensate locally, reducing overall complexity compared to a uniform design.
3Reliability
If a molding layer is added to surround chips and interposers, then warpage control and reliability are improved, but manufacturing complexity increases
Solution Approach 1:
The molding layer is integrated with the interposers and semiconductor chips to form a unified package structure. This merging provides warpage control and mechanical protection while allowing for streamlined manufacturing processes, reducing the impact of added complexity.
Data Source
AI summary
In some embodiments, a semiconductor package includes a package substrate, a plurality of semiconductor chips on the package substrate, a plurality of interposers between the package substrate and the plurality of semiconductor chips, and a molding layer in contact with the plurality of semiconductor chips and the plurality of interposers. The plurality of semiconductor chips includes a first semiconductor chip, and a second and a third semiconductor chip spaced apart from the first semiconductor chip in horizontal directions. The plurality of interposers includes a first vertical connection interposer vertically overlapping the first semiconductor chip, a second vertical connection interposer vertically overlapping the second semiconductor chip, a first horizontal connection interposer vertically overlapping the first and the second semiconductor chips, and a second horizontal connection interposer vertically overlapping the second and the third semiconductor chips.