Multi-I/O SPI Mode Removes Bit Scrambling for Precision Converters
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The JEDEC standard for flash memory communication requires bit scrambling when using multiple data lines, which is computationally expensive and impractical for devices that do not natively support the standard, leading to communication inefficiencies and potential miscommunications.
Innovation Solution
A Multi-I/O SPI mode that removes the bit scrambling requirement, allowing each bidirectional data line to be associated with a specific channel, enabling efficient communication with devices that do not support the JEDEC standard by using a special mode that synchronizes internal clock signals and multiplexes data lines, and dividing registers into primary and secondary regions for controlled access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bit scrambling is implemented according to JEDEC standard when using multiple data lines, then communication compatibility with JEDEC standard devices is improved, but computational overhead and complexity increase significantly
Solution Approach 1:
The system dynamically switches between JEDEC standard mode with bit scrambling and a simplified mode without bit scrambling based on the communication requirements and device compatibility needs, allowing adaptive optimization of computational overhead versus compatibility
Solution Approach 2:
The patent changes the bit scrambling parameter from enabled to disabled depending on the communication scenario, allowing the system to operate in JEDEC standard compliant mode when needed and in a simplified high-performance mode when communicating with non-JEDEC devices
2Productivity
If bit scrambling is removed to reduce computational overhead, then communication efficiency with non-JEDEC devices is improved, but compatibility with JEDEC standard devices deteriorates
Solution Approach 1:
The SPI interface is designed to support multiple communication modes universally, functioning both as a JEDEC standard compliant interface and as a simplified interface for non-JEDEC devices, making it adaptable to different communication partners without requiring separate hardware solutions
3Productivity
If bidirectional data lines are used to increase data transmission capacity, then communication bandwidth is improved, but risk of miscommunication increases when bit scrambling is not properly implemented
Solution Approach 1:
The patent introduces a mode selection mechanism that acts as an intermediary between the data lines and the processing logic, ensuring that when bidirectional data lines are used without bit scrambling, the system is explicitly configured to handle the data format appropriately, preventing miscommunication
Data Source
AI summary
A Multi-I/O SPI for precision converters supports a Dual/Quad/Octal SPI to support the speed requirements for digital transmission and also includes a special mode that can be enabled by hardware and/or software to remove the bit scrambling requirement dictated by the JEDEC standard. The special mode removes the scramble requirement and associates each of the bidirectional data lines to a specific channel. The special mode provides backward compatibility that permits the precision converter to be used with controllers that do not natively support the JEDEC standard. Also, the Multi-I/O SPI includes registers divided into a primary region that is accessed only in default mode at power-up for write and/or read operations, and a secondary region that is accessed by any mode enabled in the control register. By restricting access to the “control” register area to a pre-defined mode in the converter at power-up, the access mode can be controlled.