Multi-Junction Diode Leakage Current Reduction
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Solution Overview
Problem
Diodes in semiconductor devices often suffer from high leakage current due to crystalline defects near isolation regions, especially in diode arrays with multiple fingers, leading to significant yield loss and instability under electrical stress.
Innovation Solution
A diode design with multiple vertical and lateral junctions is implemented, utilizing high dopant concentration implants to minimize interaction with isolation region edges and incorporating a low dopant concentration region between the anode active area and isolation region, along with counter-doping to enhance stability and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional diode designs are used in semiconductor fabrication processes customized for high voltage FET devices, then the fabrication process can be simplified, but the diodes suffer from high leakage current due to crystalline defects near isolation regions
Solution Approach 1:
The patent applies local quality by creating a specialized diode structure with distinct doped regions (n-type and p-type regions) positioned at specific locations within the semiconductor substrate. The diode includes an n-type region, a p-type region, and additional n-type regions with different doping concentrations, where each region has locally optimized properties to prevent breakdown and reduce leakage current while maintaining compatibility with high voltage FET fabrication processes
2Reliability
If high dopant concentration implants are used to reduce leakage current, then diode stability improves, but interaction with isolation region edges increases causing crystalline defects
Solution Approach 1:
The patent introduces intermediary n-type regions with lower doping concentrations that act as buffers between the high dopant concentration implants and the isolation region edges. These intermediate regions reduce the direct interaction and stress concentration at the isolation region boundaries, thereby minimizing crystalline defects while still providing the stability benefits of doped structures
Solution Approach 2:
The patent employs parameter changes by varying the doping concentrations across different regions of the diode structure. Specifically, it uses regions with different n-type doping concentrations (heavily doped, moderately doped, and lightly doped regions) to optimize the electrical characteristics and mechanical stress distribution, reducing crystalline defects at isolation region edges
3Reliability
If multiple dopant implantation procedures are implemented to create customized diode features, then diode performance improves, but fabrication costs and process complexity increase
Solution Approach 1:
The patent achieves universality by designing a diode structure that can be fabricated using the same dopant implantation procedures and process steps used for high voltage FET devices. The multi-region doped structure serves multiple functions: it creates the diode junction, provides breakdown protection, reduces leakage current, and maintains compatibility with existing high voltage device fabrication workflows, eliminating the need for separate customized processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The diode design significantly reduces leakage current and improves stability under electrical stress, minimizing yield loss and enhancing operational reliability.
Implementation Method 1
performing a dopant implantation procedure to form a first well region disposed in the semiconductor substrate
Data Source
AI summary
A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface.