Multi-Kernel Circuit Design Performance Prediction Using Programmable Pattern Generators
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Solution Overview
Problem
Current methods for predicting the performance of multi-kernel circuit designs in integrated circuits (ICs) are overly optimistic for single kernels but degrade when multiple kernels compete for memory resources, leading to suboptimal overall system performance, requiring lengthy design flows and iterations for verification.
Innovation Solution
A method that determines memory access patterns of multiple kernels and generates different floorplans specifying memory interface mappings and kernel allocations to programmable pattern generator circuit blocks, allowing for execution and selection based on performance metrics to optimize memory access patterns without full design flow processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If computer-based implementation tools are used to estimate performance of individual kernels, then the estimation process is automated and efficient, but the performance estimates become overly optimistic when multiple kernels compete for memory resources
Solution Approach 1:
The patent introduces an intermediary simulation environment that models the actual IC architecture including memory resources and interconnects. This intermediary layer between the performance estimation tool and the actual implementation allows realistic performance prediction without requiring full design flow processing, thus maintaining efficiency while improving accuracy.
Solution Approach 2:
The patent creates a simplified copy or model of the IC architecture that replicates the essential memory access patterns and resource contention scenarios. This architectural model allows performance estimation to be conducted in a realistic environment that captures multi-kernel interactions without the complexity and time cost of complete implementation and verification.
2Adaptability or versatility
If multiple kernels are implemented concurrently in the IC, then the system functionality is enhanced, but the overall system performance degrades due to memory resource competition
Solution Approach 1:
The patent performs preliminary performance analysis and memory access pattern characterization during the design phase, before final implementation. By identifying potential resource contention scenarios in advance and optimizing memory interface mappings and kernel allocations upfront, the system achieves both multi-kernel functionality and acceptable performance without requiring lengthy iterative verification.
3Manufacturing precision
If complete design flow processing is performed for verification, then design accuracy is ensured, but the design process becomes lengthy and iterative
Solution Approach 1:
The patent performs preliminary performance analysis and memory access pattern characterization during the design phase, before final implementation. By identifying potential resource contention scenarios in advance and optimizing memory interface mappings and kernel allocations upfront, the system achieves both multi-kernel functionality and acceptable performance without requiring lengthy iterative verification.
Solution Approach 2:
The patent creates a simplified copy or model of the IC architecture that replicates the essential memory access patterns and resource contention scenarios. This architectural model allows performance estimation to be conducted in a realistic environment that captures multi-kernel interactions without the complexity and time cost of complete implementation and verification.
Data Source
AI summary
Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of different floorplans are executed using the circuit architecture in the IC. The plurality of PPG circuit blocks mimic the memory access patterns of the kernels for each of the plurality of different floorplans during the executing. One or more design constraints are generated based on a selected floorplan. The selected floorplan is selected from the plurality of different floorplans based on one or more performance metrics determined from the executing.