Multi-Lane Encryption Circuitry for Channel Adaptability
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Solution Overview
Problem
Existing encryption and authentication circuitry faces challenges when the number of channels exceeds the number of lanes or when the data rate exceeds device speed, leading to complications in delivering the correct encryption or hash keys to the correct lane at the correct time, especially in unknown encryption applications.
Innovation Solution
The proposed solution involves multi-lane encryption and authentication circuitry with a fixed size, including a certain number of lanes and stages per lane, capable of supporting a maximum number of channels. Each lane can select the appropriate encryption key for the channel it operates on, and partial hash states are calculated and combined to generate the final hash state, with wind-down mode detection to manage multiple partial hashes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of lanes is fixed, then the device complexity is reduced, but the adaptability to different channel configurations deteriorates
Solution Approach 1:
The encryption circuitry is divided into multiple independent stages, with each stage capable of processing a subset of channels. This segmentation allows the fixed physical structure to flexibly accommodate variable channel configurations by activating different stage combinations based on the number of channels being processed.
Solution Approach 2:
The circuitry incorporates dynamic control mechanisms that allow each stage to be independently enabled or disabled based on the current channel configuration. This dynamic adaptability enables the fixed device to efficiently handle varying numbers of channels without requiring physical reconfiguration.
2Productivity
If multiple lanes are used to increase throughput, then the productivity is improved, but the difficulty of delivering correct keys to correct lanes deteriorates
Solution Approach 1:
Keys are pre-distributed to appropriate stages before encryption processing begins. Each stage receives and stores the keys it will need for its specific channel assignments, eliminating the complexity of real-time key routing across multiple lanes during the encryption process.
Solution Approach 2:
A key management intermediary structure is implemented that acts as a buffer between key sources and multiple encryption lanes. This intermediary systematically routes keys to the correct lanes based on channel assignments, simplifying the overall key delivery mechanism while supporting high-throughput multi-lane operation.
3Adaptability or versatility
If the number of channels exceeds the number of lanes, then the adaptability is improved, but the time required for encryption processing increases
Solution Approach 1:
The encryption process is divided into multiple sequential stages, each handling a manageable subset of channels. This segmentation allows channels to be processed in organized batches across available lanes, preventing any single lane from becoming a bottleneck while maintaining efficient utilization of all available processing resources.
Solution Approach 2:
The multi-stage architecture enables continuous processing where while some lanes are completing encryption for one set of channels, other lanes simultaneously begin processing the next set of channels. This continuous operation minimizes idle time and maintains high throughput even when channels exceed the number of physical lanes.
Data Source
AI summary
Encryption/authentication circuitry includes an authentication portion operating on a plurality of lanes of encrypted data spanning a number of channels, and including hash constant storage for a predetermined maximum number of channels, and partial hash selection circuitry for determining, for each respective lane, a respective hash index into the hash constant storage. Wind-down mode detection circuitry also is described, as well as a method of operating such circuitry also is provided.