Multi-Lane FEC Frame Distribution for High-Speed Mobile Links

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Solution Overview

Problem

Existing interconnection protocols, such as MIPI M-PHY and UniPro, face challenges in achieving high-speed data transmission with low power consumption and effective error correction, particularly in mobile devices, due to limitations in line encoding schemes and error detection/correction mechanisms.

Innovation Solution

Implementing a forward error correction (FEC) frame with a multi-way interleaved scheme and adaptive lane distribution orders based on the number of active lanes, combined with advanced signaling schemes like PAM-n, to enhance data throughput and reduce re-transmission rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If 8b10b coding scheme is used for line encoding, then DC balance is achieved, but data transmission rate is reduced due to 20% overhead

Engineering Contradiction:
ImproveDC balanceVSAvoiddata transmission rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the encoding parameters from traditional 8b10b (8 data bits + 2 balance bits) to 1b1b (1 data bit + 1 balance bit) with modified coding rules. This parameter change eliminates the 20% overhead while maintaining DC balance through alternative coding mechanisms that track running disparity without requiring additional balance bits for every byte.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If multiple lanes are used for high-speed transmission, then data throughput is improved, but error detection and correction becomes more complex

Engineering Contradiction:
Improvedata throughputVSAvoiderror detection and correction mechanism
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the multi-lane transmission into independent error detection units, where each lane has its own error detection capability. The FEC frame structure divides data into multiple blocks that can be independently processed, allowing parallel error detection across lanes without requiring complex centralized correction mechanisms.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces FEC frames as an intermediary structure that encapsulates data blocks with associated error detection and correction information. This intermediary layer simplifies the error handling process by providing a standardized format that works across multiple lanes without requiring complex lane-specific correction logic.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If FEC frames are distributed over multiple lanes, then data rate is improved, but lane configuration adaptability is reduced

Engineering Contradiction:
Improvedata rateVSAvoidlane configuration adaptability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic lane distribution where the FEC frame distribution pattern can be selectively changed based on the number of active lanes. The system can adapt between different lane configurations (e.g., 1 lane, 2 lanes, 4 lanes) by selecting appropriate distribution orders, making the high-speed transmission mechanism flexible rather than fixed to a specific lane count.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12549280B2Electronic device and operation method therefor
Publication Date: 2026.02.10 SK HYNIX INC
  • US12549280B2 patent drawing
  • US12549280B2 patent drawing
  • US12549280B2 patent drawing

AI summary

Electronic device and operation method therefor are provided. The electronic device is operable to communicate with another electronic device. The operation method comprises the following operations. A forward error correction (FEC) frame to be transmitted via a plurality of active lanes of a link is obtained, wherein the FEC frame includes a data block, an error detection block associated with the data block, and an error correction block associated with the data block and the error detection block. The FEC frame is distributed over the lanes of the link in one of a plurality of different lane distribution orders selectively based on number of active lanes included in the plurality of active lanes. The FEC frame is transmitted over the plurality of lanes of the link to another electronic device.