Multi-Lane Memory Compression for Lower Cache Swap Latency
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Solution Overview
Problem
In computing systems, the limited storage capacity of local cache memories leads to significant latency and performance reduction due to frequent swapping of data between cache and persistent storage, especially when handling multiple software applications, as the central processing unit (CPU) is often the sole processor for data compression and decompression, causing delays for other processors.
Innovation Solution
A processor core with an integrated compression/decompression unit that offloads compression and decompression tasks from the CPU, utilizing multiple hardware lanes and dictionary-based algorithms for parallel processing, allowing other processors to continue operations while data is compressed or decompressed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data compression is performed using the CPU, then compression functionality is available, but the CPU becomes unavailable for other processing tasks causing delays
Solution Approach 1:
The patent extracts the compression and decompression functionality from the CPU by implementing dedicated compression logic within the network interface card (NIC). This allows the CPU to offload these specific tasks to the NIC's integrated compression engine, thereby maintaining CPU availability for other processing tasks while preserving compression capabilities.
2Loss of time
If local cache memory storage capacity is increased, then data swapping latency is reduced, but memory cost and device complexity increase
Solution Approach 1:
The patent applies data compression to change the size parameter of stored data, allowing more data to be held in the existing local cache memory without increasing its physical capacity. By compressing data before storage and decompressing when needed, the system effectively increases storage density and reduces the frequency of data swapping operations, thereby reducing latency without adding more memory.
3Quantity of substance
If data compression is used to reduce storage requirements, then storage capacity is optimized, but additional compression and decompression processing time is required
Solution Approach 1:
The patent implements self-service compression by integrating the compression engine directly into the NIC, allowing data to be compressed and decompressed automatically as part of the network I/O operations without requiring explicit CPU intervention. This automated approach minimizes the overhead associated with compression by making it a transparent part of the data path.
Solution Approach 2:
The patent replaces software-based compression (which would consume CPU cycles) with hardware-based compression logic integrated into the NIC. This substitution moves the compression function from the software/CPU domain to the hardware/NIC domain, significantly reducing the processing time overhead by parallelizing compression with other I/O operations.
4Device complexity
If the CPU is the only processor supporting compression operations, then implementation simplicity is maintained, but other processors incur delays waiting for CPU availability
Solution Approach 1:
The patent enhances the NIC's functionality by integrating multiple capabilities into a single device: network interface operations, data compression, and decompression. This multi-functional NIC can service multiple processors simultaneously, allowing any processor in the system to utilize the NIC's compression engine without requiring CPU involvement, thereby eliminating delays for multi-processor systems.
Data Source
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AI summary
Systems, apparatuses, and methods for efficiently moving data for storage and processing are described. In various embodiments, a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.