Multi-Lane Data Receiver Phase Alignment With Fewer Delay Circuits
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Solution Overview
Problem
Existing high-speed interface standards for mobile and camera devices, such as the C-PHY and D-PHY standards, face increased circuit scale and power consumption when multiple data lanes are used, as they require multiple delay circuits for phase adjustment between clock and data signals.
Innovation Solution
A data receiving apparatus with a first phase adjustment circuit for synchronizing multiple data signals and a second phase adjustment circuit for synchronizing the clock signal with the data signals, reducing the need for redundant delay circuits and minimizing circuit scale and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a delay circuit is provided between each data lane and clock lane for phase adjustment, then phase alignment between clock signal and data signal is achieved, but circuit scale and power consumption increase as the number of data lanes increases
Solution Approach 1:
The patent merges the phase adjustment functions by providing a single delay circuit in the data signal line instead of separate delay circuits for each lane. This consolidation maintains phase alignment capability while reducing the overall circuit scale and power consumption that would otherwise increase with the number of data lanes.
Solution Approach 2:
The delay circuit is designed to handle phase adjustment for multiple data lanes universally. By making the delay circuit multi-functional, it can service all data lanes without requiring dedicated delay circuits for each lane, thus achieving phase alignment across multiple lanes while keeping the circuit scale manageable.
2Manufacturing precision
If a delay circuit is provided between each data lane and clock lane for phase adjustment, then phase alignment between clock signal and data signal is achieved, but power consumption increases as the number of data lanes increases
Solution Approach 1:
The patent merges the phase adjustment functions by providing a single delay circuit in the data signal line instead of separate delay circuits for each lane. This consolidation maintains phase alignment capability while reducing the overall circuit scale and power consumption that would otherwise increase with the number of data lanes.
3Adaptability or versatility
If multiple delay circuits are provided for multiple data lanes, then phase adjustment is performed for each lane, but the number of circuit elements increases
Solution Approach 1:
The delay circuit is designed to handle phase adjustment for multiple data lanes universally. By making the delay circuit multi-functional, it can service all data lanes without requiring dedicated delay circuits for each lane, thus achieving phase alignment across multiple lanes while keeping the circuit scale manageable.
Data Source
AI summary
A data receiving apparatus of the present disclosure includes a first phase adjustment circuit and a second phase adjustment circuit. The first phase adjustment circuit performs a phase adjustment between multiple data signals received via multiple data signal lines. The second phase adjustment circuit performs a phase adjustment of a clock signal received via a clock signal line with respect to the multiple data signals after the phase adjustment between the multiple data signals is performed by the first phase adjustment circuit.