Multi-Lane Ethernet Packet Timestamping With Phase-Offset Compensation
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Solution Overview
Problem
Existing time stamping methods for packets in multi-lane Ethernet ports suffer from inaccuracies due to alignment marker/codeword insertion, RS-FEC delay variations, and de-skew buffer alignment issues, which are critical for achieving nanosecond accuracy required in 5G networks and time-sensitive applications.
Innovation Solution
Adjust the time stamp by accounting for delays associated with signal manipulations, using a single phase measurement device for the last arriving lane, and compensating for phase offsets and SFD positions across multiple lanes to improve accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If time stamping is performed at multi-lane Ethernet ports, then packet transmission/reception timing can be recorded, but accuracy is degraded due to alignment marker insertion, RS-FEC delay variations, and de-skew buffer alignment issues
Solution Approach 1:
The patent applies preliminary action by measuring the phase offset between the recovered clock signal and system clock signal before time stamping occurs. The system determines this phase offset in advance and uses it to adjust the time stamp value, thereby compensating for timing errors introduced by multi-lane processing, alignment markers, and de-skew buffers before they affect the final time stamp accuracy.
2Reliability
If alignment markers and RS-FEC are used in multi-lane ports, then signal integrity and synchronization are improved, but time stamp accuracy is degraded due to additional delays and variations
Solution Approach 1:
The patent implements feedback by using the measured phase offset information to adjust and compensate the time stamp value. The system continuously monitors the phase relationship between recovered and system clocks, and feeds this information back into the time stamping mechanism to correct for delays introduced by alignment markers and RS-FEC processing, thereby maintaining both signal reliability and time stamp precision.
3Stability of the object's composition
If de-skew buffers are used to align lanes, then lane synchronization is improved, but time stamp accuracy is degraded due to buffer alignment issues and variable delays
Solution Approach 1:
The patent introduces an intermediary approach by using phase offset measurement as a mediating parameter between the de-skew buffer alignment process and the final time stamp. Instead of directly measuring packet arrival time after buffer processing (which introduces errors), the system measures the phase relationship between clock signals as an intermediary indicator, which then informs the correction of time stamp values to account for buffer-induced delays.
Data Source
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AI summary
In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.