Multi-lateral Recessed MIM Capacitor Structure
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Solution Overview
Problem
MIM capacitors in integrated chips consume a large footprint to achieve desired capacitance, making them expensive and inefficient as feature sizes decrease, as they cannot scale in size without reducing capacitance.
Innovation Solution
A metal-insulator-metal (MIM) capacitor structure with a variable width is implemented, where the dielectric stack has interleaved layers of different etching rates, creating serrated profiles that increase the surface area of the electrodes, thereby enhancing capacitance without increasing the overall footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional MIM capacitor structure with straight sidewalls is used, then manufacturing is simple, but capacitance per footprint area is low
Solution Approach 1:
The patent transitions from a 2D planar capacitor structure to a 3D vertically extended structure with multiple tiers and stacked dielectric layers. This dimensional change allows the capacitor to achieve higher capacitance density by utilizing vertical space, effectively reducing the footprint area required for the same capacitance value while maintaining manufacturing feasibility through sequential deposition processes.
Solution Approach 2:
The patent implements a nested structure where multiple dielectric layers and conductive electrodes are stacked vertically within each other, forming a multi-tiered capacitor. Each tier contains nested layers of dielectric materials and conductive elements, maximizing the use of vertical space to increase capacitance without proportionally increasing the horizontal footprint area.
2Productivity
If feature sizes decrease, then integration density improves, but MIM capacitor capacitance reduces
Solution Approach 1:
As feature sizes decrease and integration density increases, the patent compensates for reduced capacitance by extending the capacitor structure vertically into the third dimension. Multiple stacked dielectric layers and conductive tiers provide increased surface area for charge storage, maintaining capacitance values even as lateral dimensions are reduced to achieve higher integration density.
Solution Approach 2:
The patent employs composite dielectric structures with multiple layers of different materials (e.g., silicon oxide, silicon nitride, low-k dielectrics) to optimize both capacitance and integration density. The composite structure allows tuning of electrical properties while maintaining compatibility with scaled feature sizes and high-density integration requirements.
3Area of stationary object
If MIM capacitor footprint is reduced, then chip area efficiency improves, but capacitance value decreases
Solution Approach 1:
The patent resolves the trade-off between chip area and capacitance value by transitioning to a vertical 3D structure. Multiple stacked tiers with interleaved dielectric and conductive layers increase the effective capacitance-generating surface area without proportionally increasing the horizontal chip footprint, thereby improving area efficiency while maintaining capacitance values.
Solution Approach 2:
The capacitor is segmented into multiple discrete tiers or stages, each contributing to the total capacitance. This segmentation allows the capacitance to be distributed across multiple vertical levels rather than requiring a single large planar structure, enabling reduced chip area while maintaining or increasing total capacitance value through the cumulative effect of multiple segments.
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric stack disposed over a substrate. The dielectric stack has a first plurality of layers interleaved between a second plurality of layers. The dielectric stack has one or more surfaces that define a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers. A capacitor structure lines the one or more surfaces of the dielectric stack. The capacitor structure includes conductive electrodes separated by a capacitor dielectric.